MT9040ANR1 datasheet, PDF - EEWORLD Datasheet

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MT9040ANR1: DescriptionSPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48; CategoryWireless rf/communication Telecom circuit; File Size264KB，26 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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SPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48

MT9040ANR1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	48
Reach Compliance Code	compliant
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	15.88 mm
Number of functions	1
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.79 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.64 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.49 mm

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MT9040

T1/E1 Synchronizer

Data Sheet

Features

•

Supports AT&T TR62411 and Bellcore GR-1244-

CORE and Stratum 4 timing for DS1 interfaces

Supports ETSI ETS 300 011, TBR 4, TBR 12 and

TBR 13 timing for E1 interfaces

Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or

8kHz input reference signals

Provides C1.5, C2, C4, C6, C8, C16, and C19

(STS-3/OC3 clock divided by 8) output clock

signals

Provides 5 different styles of 8 KHz framing

pulses

Attenuates wander from 1.9 Hz

Fast lock mode

JTAG Boundary Scan

Ordering Information

MT9040AN

48 Pin SSOP

MT9040ANR

48 Pin SSOP

MT9040AN1

48 Pin SSOP*

MT9040ANR1 48 Pin SSOP*

*Pb Free Matte Tin

-40°C to +85°C

Tubes

Tape & Reel

Tubes

Tape & Reel

February 2009

Description

The MT9040 T1/E1 System Synchronizer contains a

digital phase-locked loop (DPLL), which provides timing

and synchronization signals for T1 and E1 primary rate

transmission links.

The MT9040 generates ST-BUS clock and framing

signals that are phase locked to either a 19.44 MHz,

2.048 MHz, 1.544 MHz, or 8 kHz input reference.

The MT9040 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS

300 011. It will meet the jitter/wander tolerance, jitter

transfer, intrinsic jitter, frequency accuracy and capture

range for these specifications.

LOCK

VDD

VSS

•

Applications

•

Synchronization and timing control for multitrunk

T1 and E1 systems

ST-BUS clock and frame pulse source

OSCi

OSCo

FLOCK

Master Clock

TCK

TDI

TMS

TRST

TDO

IEEE

1149.1a

DPLL

Output

Interface

Circuit

Input

Impairment

Monitor

REF

C19o

C1.5o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

TSP

Control State Machine

Feedback

Frequency

Select

MUX

RST

FS1

FS2

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT9040

Data Sheet

Phase Detector

- the Phase Detector compares the reference signal with the feedback signal from the Frequency

Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error

signal is passed to the Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally

selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).

Reference

Phase

Detector

Loop Filter

Digitally

Controlled

Oscillator

DPLL Reference

Output Interface Circuit

Feedback Signal

from

Frequency Select MUX

State Select

from

Input Impairment Monitor

Control

Circuit

State Select

from

State Machine

Figure 3 - DPLL Block Diagram

Loop Filter

- the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four

reference frequency selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the network

jitter transfer requirements are met.

Control Circuit

- the Control Circuit uses status and control information from the State Machine and the Input

Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.

Digitally Controlled Oscillator (DCO)

- the DCO receives the filtered signal from the Loop Filter, and based on its

value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on

the state of the MT9040.

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the input reference

signal.

In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.

Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to

the line frequency), and the input phase offset is small, then the lock signal will be set high. For specific Lock

Indicator design recommendations, see the Applications - Lock Indicator section.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure

4. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,

and a DS2 Divider Circuit to generate the required output signals.

Four tapped delay lines are used to generate 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.

The E1 Divider Circuit uses the 16.38 4MHz signal to generate four clock outputs and five frame pulse outputs. The

C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.

These outputs have a nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384 MHz signal to generate the C1.5o clock by dividing the internal C12 clock

by eight. This output has a nominal 50% duty cycle.

The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal

50% duty cycle.

Zarlink Semiconductor Inc.

MT9040ANR1 Related Products

	MT9040ANR1	MT9040AN	MT9040AN1	MT9040ANR
Description	SPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48	SPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, MO-118AA, SSOP-48	SPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48	SPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, MO-118AA, SSOP-48
Is it Rohs certified?	conform to	incompatible	conform to	incompatible
Maker	XILINX	XILINX	XILINX	XILINX
Parts packaging code	SSOP	SSOP	SSOP	SSOP
package instruction	SSOP,	SSOP,	SSOP,	SSOP,
Contacts	48	48	48	48
Reach Compliance Code	compliant	compliant	compliant	compliant
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
length	15.88 mm	15.88 mm	15.88 mm	15.88 mm
Number of functions	1	1	1	1
Number of terminals	48	48	48	48
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP	SSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.79 mm	2.79 mm	2.79 mm	2.79 mm
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.64 mm	0.64 mm	0.64 mm	0.64 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.49 mm	7.49 mm	7.49 mm	7.49 mm

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