IDT70V7519S133BFGI8 datasheet, PDF

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IDT70V7519S133BFGI8: DescriptionDual-Port SRAM, 256KX36, 15ns, PBGA208, FBGA-208; Categorystorage storage; File Size491KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70V7519S133BFGI8 Overview

Dual-Port SRAM, 256KX36, 15ns, PBGA208, FBGA-208

IDT70V7519S133BFGI8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	15 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	9437184 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX36
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm

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HIGH-SPEED 3.3V 256K x 36

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

IDT70V7519S

256K x 36 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–

64 independent 4K x 36 banks

– 9 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns

(133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Functional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

4Kx36

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-35L

I/O

CONTROL

MUX

4Kx36

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-35R

11L

ADDRESS

DECODE

ADDRESS

DECODE

11R

BANK

DECODE

MUX

4Kx36

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5618 drw 01

DECEMBER 2002

DSC 5618/5

IDT70V7519S133BFGI8 Related Products

	IDT70V7519S133BFGI8	IDT70V7519S166BFG8	IDT70V7519S133BCG8	IDT70V7519S133BCGI8	IDT70V7519S166BCG8	IDT70V7519S166BCGI8	IDT70V7519S133BFG8
Description	Dual-Port SRAM, 256KX36, 15ns, PBGA208, FBGA-208	Dual-Port SRAM, 256KX36, 12ns, PBGA208, FBGA-208	Dual-Port SRAM, 256KX36, 15ns, PBGA256, BGA-256	Dual-Port SRAM, 256KX36, 15ns, PBGA256, BGA-256	Dual-Port SRAM, 256KX36, 12ns, PBGA256, BGA-256	Dual-Port SRAM, 256KX36, 12ns, PBGA256, BGA-256	Dual-Port SRAM, 256KX36, 15ns, PBGA208, FBGA-208
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA,	TFBGA,	LBGA,	LBGA,	LBGA,	LBGA,	TFBGA,
Contacts	208	208	256	256	256	256	208
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	15 ns	12 ns	15 ns	15 ns	12 ns	12 ns	15 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PBGA-B208	S-PBGA-B208	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B208
JESD-609 code	e1	e1	e1	e1	e1	e1	e1
length	15 mm	15 mm	17 mm	17 mm	17 mm	17 mm	15 mm
memory density	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	36	36	36	36	36	36	36
Humidity sensitivity level	3	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1	1
Number of terminals	208	208	256	256	256	256	208
word count	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C	70 °C	85 °C	70 °C
organize	256KX36	256KX36	256KX36	256KX36	256KX36	256KX36	256KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	LBGA	LBGA	LBGA	LBGA	TFBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.2 mm
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	1 mm	1 mm	1 mm	1 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
width	15 mm	15 mm	17 mm	17 mm	17 mm	17 mm	15 mm

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