BU-65743/65843/65863/65864
PCI MINI-ACE
®
MARK3 AND
Make sure the next
Card you purchase
has...
®
PCI MICRO-ACE
®
*-TE
FEATURES
•
32-Bit/33MHz, 3.3Volt, PCI Target
Interface
•
Fully Integrated 1553A/B Notice 2,
1760, McAir, STANAG 3838 Interface
Terminal
•
All +3.3V Operation or +3.3V Logic
and +5V Transceivers
•
0.88 inch square, 80-Pin CQFP (PCI
Mini-ACE Mark3) or 0.80 inch square
324 ball BGA (PCI Micro-ACE TE)
•
Compatible with PCI Enhanced Mini-
ACE, Enhanced Mini-ACE, Mini-ACE
and ACE Generations
•
Choice of :
-
RT only with 4K RAM (BU-65743)
- BC/RT/MT with 4K RAM (BU-65843)
- BC/RT/MT with 64K RAM, and RAM
Parity (BU-65863, BU-65864)
•
Sleep Mode Option
•
Choice of 10, 12, 16, or 20 MHz 1553
Clock
•
Highly Autonomous BC with Built-In
Message Sequence Control:
- Frame Scheduling
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
•
Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
•
Selective Message Monitor or
RT/Monitor
FOR MORE INFORMATION CONTACT:
DESCRIPTION
The PCI Mini-ACE Mark3/Micro-ACE TE family of MIL-STD-1553 terminals
provides a complete interface between a 32-Bit/33Mhz 3.3V signaling PCI Bus
and a MIL-STD-1553 bus. These terminals integrate dual transceiver, protocol
logic, and 4K or 64K words of RAM, all of which can be powered from 3.3V.
With a 0.88-inch square package, the PCI Mini-ACE Mark3 is the smallest
ceramic CQFP PCI 1553 solution available. The 0.80-inch square 324 ball BGA
PCI Micro-ACE TE has an even smaller footprint, but has a more restricted
operating temperature range. Both are 100% software compatible with the
larger PCI Enhanced Mini-ACE and add TAG_CLK inputs. The TAG_CLK input
allows a software selectable external time tag clock input. Both parts are avail-
able with a choice of either 3.3V transceivers or 5V transceivers.
The PCI Micro-ACE TE has a more restricted set of options compared to the
PCI Mini-ACE Mark3. Please consult the ordering information at the rear of the
data sheet to see which options are available. In addition, the PCI Micro-ACE
TE adds RTBOOT and 1553 clock select inputs for applications which must
boot into RT mode with Busy bit set.
The PCI Mini-ACE Mark3/Micro-ACE TE is nearly 100% software compatible
with the Enhanced Mini-ACE and previous generation Mini-ACE terminals. The
PCI interface to this terminal is not 5V tolerant.
Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, including
Mark3 versions incorporating McAir compatible transmitters, is provided. There
is a choice of 10, 12, 16, or 20 MHz 1553 clocks. The BC/RT/MT versions with
64K words of RAM include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with a set of
20 instructions. This provides an autonomous means of implementing multi-
frame message scheduling, message retry schemes, data double buffering,
asynchronous message insertion, and reporting to the host CPU.
The PCI Mini-ACE Mark3 and Micro-ACE TE RT offer single and circular sub-
address buffering schemes, along with a global circular buffering option, 50%
rollover interrupt for circular buffers, and an interrupt status queue.
Technical Support:
1-800-DDC-5757 ext. 7771
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
*
©
The technology used in DDC’s Micro-ACE series of products may be
subject to one or more patents pending.
All trademarks are the property of their respective owners.
2003 Data Device Corporation
Data Device Corporation
www.ddc-web.com
4K X 16
OR
64K X 17
SHARED
RAM
32 X 32
WRITE
FIFO
TRANSCEIVER
A
AD31-AD0
DATA BUS
PAR
C/BE#3 - C/BE#0
ADDRESS BUS
33 MHZ,
32-BIT
PCI SLAVE
INTERFACE
PCI Address/Data, Parity
and Bus Command/Byte Enable
TX/RX_A
(1:2.038)
CH. A
TX/RX_A
TX_INH A/B
•
•
TRANSCEIVER
B
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
(1:2.038)
CH. B
FRAME#, IRDY#,IDSEL
TRDY#, STOP#, DEVSEL#,
PERR#, SERR#
PCI Control
2
RTAD4-RTAD0, RTADP
RT-AD4-LAT
INCMD/MCRST
1553_CLK, SSFLAG/EXT_TRIG,TAG_CLK
BOOT_L,CLK_SEL_0/1 (Micro-ACE TE ONLY)
NOTE 1: Shown with 3.3V transceivers. 5V transceivers are available.
TX/RX_B
(PCI) CLK
PCI CLK
RT ADDRESS AND
ADDRESS LATCH
INT A #
PCI Interrupt
MISCELLANEOUS
MSTCLR (RST#)
BU-65743/65843/65863/65864
AC-6/11-0
FIGURE 1. PCI MINI-ACE MARK3/MICRO-ACE TE (3.3V TRANSCEIVERS) BLOCK DIAGRAM
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
•
Logic +3.3V
•
Transceiver +3.3V
(BU65XX3X8/9)
•
Transceiver +5V(BU-65XX3F3/4,
BU-65XX3G3/4, BU-658XXB3)
Logic
•
Voltage Input Range
•
Voltage Input Range,
+5V Tolerant Pins (Note 16)
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6, 19)
Threshold Voltage, Transformer
Coupled
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
•
Direct Coupled Across 35
Ω,
Measured on Bus
•
Transformer Coupled Across
70
Ω,
Measured on Bus
(BU-65XXXXX-XX0,
BU-65XXXXX-XX2) (Note 13)
Output Noise, Diff (Direct Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
(BU-65XXXX3,
BU-65XXXX4)
LOGIC
V
IH
All signals except PCI, SLEEP_
IN
V
IL
All signals except PCI, SLEEP_
IN
Schmidt Hysteresis
All signals except PCI
I
IH,
I
IL
All signals except PCI, SLEEP_
IN
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IN
=2.7V)
I
IL
(Vcc=3.6V, V
IN
=0.4V)
V
IH
SLEEP_IN (Vcc=3.6V)
V
IL
SLEEP_IN (Vcc=3.0V)
I
IH,
I
IL
SLEEP_IN
I
IH
(Vcc=3.6V, V
IN
=2.7V)
I
IL
(Vcc=3.6V, V
IN
=0.0V)
V
OH
(Vcc=3.0V, I
OH=max
)
V
OL
(Vcc=3.0V, I
OL=max
)
I
OL
I
OH
C
I
(Input Capacitance)
PCI LOGIC see PCI spec 3.3V
signaling environment
C
I
(Input Capacitance) all PCI
except PCI_CLK & IDSEL
C
I
(Input Capacitance) PCI_CLK
C
I
(Input Capacitance) IDSEL
MIN
TYP
MAX
UNITS
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
PARAMETER
POWER SUPPLY REQUIREMENTS
(3.3V TRANSCEIVER)
Voltages/Tolerances
•
+3.3V
Current Drain (Total Hybrid)
(Note 17)
•
BU-65863F(G)8(9)-XX0
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-65863F(G)8-XX2,
BU-65863B(R)8-E02
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-65843F(G)8(9)-XX0,
BU-65743F(G)8(9)-XX0
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-65743F(G)8-XX2,
BU-65843X8(R)-XX2
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION (NOTES 17-18)
Total Hybrid (3.3V Transceiver)
•
BU-65863X8(9)-XX0
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-65863F(G)8-XX2,
BU-65863B8-E02
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
4.0
4.5
7.0
V
V
V
V
V
3.15
3.3
3.45
V
31
77
267
457
837
27
76
242
383
725
16
56
246
436
816
12
55
221
362
704
67
110
315
515
915
67
110
335
535
995
52
95
300
500
900
52
95
320
520
980
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Vdd+0.3
6.0
2.5
50
0.200
0.860
10
kΩ
pF
Vp-p
Vpeak
6
7
9
Vp-p
18
20
-250
100
200
20
21.5
150
150
250
27
27
10
250
300
300
Vp-p
Vp-p
mVp-p
mV
p
ns
ns
2.1
0.7
0.4
V
V
V
0.10
0.25
0.62
0.97
1.64
0.10
0.25
0.64
1.00
1.73
0.22
0.36
0.74
1.09
1.79
0.22
0.36
0.76
1.13
1.88
W
W
W
W
W
W
W
W
W
W
-10
-100
-100
2.5
10
-20
2.4
3.4
10
-33
-33
0.9
70
+20
0.4
-3.4
20
µA
µA
µA
V
V
µA
µA
V
V
mA
mA
pF
10
4
6
pF
pF
pF
Data Device Corporation
www.ddc-web.com
3
BU-65743/65843/65863/65864
AC-6/11-0
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
PARAMETER
POWER DISSIPATION (NOTES 17-18)
Total Hybrid (3.3V Transceiver)
(CONT)
•
BU-65743F(G)8(9)-XX0,
BU-65843F(G)8(9)-XX0
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-65743F(G)8-XX2,
BU-65843F(G)8-XX2,
BU-65843B8-E02
• Idle w/ transceiver SLEEPIN
asserted
• Idle w/ transceiver SLEEPIN
negated
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
HOTTEST DIE (3.3V TRANSCEIVER)
•
BU-65XXXX8(9)-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-65XXXX8-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER SUPPLY REQUIREMENTS
(5V TRANSCEIVER)
Voltages/Tolerances
+3.3V (Logic) V
CC
+5V (XCVR or 5V V
CC
CHA/B)
+5V (RAM for BU-65864B(R)3)
Current Drain (Total Hybrid)
•
BU-65863F(G)3(4)-XX0
+5V (XCVR)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
+3.3V (Logic)
•
BU-65863F(G)3-XX2
+5V (XCVR)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
+3.3V (Logic)
•
BU-65864B(R)3-E02
+5V (RAM, CHA, CHB)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
+3.3V (Logic)
MIN
TYP
MAX
UNITS
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
PARAMETER
POWER SUPPLY REQUIREMENTS
(5V TRANSCEIVER)(CONT)
• BU-65743F(G)3(4)-XX0,
BU-65843F(G)3(4)-XX0
+5V (XCVR)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
+3.3V (Logic)
• BU-65743F(G)3-XX2,
BU-65843F(G)3-XX2,
BU-65843B3-E02
+5V (XCVR or 5V ChA, 5V Ch B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
+3.3V (Logic)
POWER DISSIPATION (NOTE 15)
TOTAL HYBRID (5V TRANSCEIVER)
• BU-65863F(G)3(4)-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-65863F(G)3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-65864B(R)3-E02
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-65743F(G)3(4)-XX0
BU-65843F(G)3(4)-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-65743F(G)3-XX2
BU-65843F(G)3-XX2,
BU-65843B3-E02
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
HOTTEST DIE (5V TRANSCEIVER)
• BU-65XXXX3(4)-xx0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-65XXXX3-xx2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX
UNITS
0.10
0.18
0.47
0.72
1.22
0.17
0.31
0.69
1.04
1.74
W
W
W
W
W
65
169
273
481
25
100
205
310
520
40
mA
mA
mA
mA
mA
0.10
0.18
0.49
0.76
1.31
0.17
0.31
0.71
1.08
1.83
W
W
W
W
W
65
180
295
525
25
100
216
332
565
40
mA
mA
mA
mA
mA
0.07
0.37
0.70
1.37
0.07
0.37
0.59
1.13
0.11
0.45
0.80
1.51
0.11
0.47
0.84
1.59
W
W
W
W
W
W
W
W
0.41
0.73
1.02
1.63
0.41
0.76
1.13
1.86
0.44
0.80
1.17
1.89
0.41
0.70
0.94
1.40
0.75
1.00
1.23
1.68
0.75
1.04
1.34
1.94
0.80
1.09
1.39
1.97
0.63
0.85
1.07
1.51
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
3.0
4.75
4.5
3.3
5.0
5.0
3.6
5.5
5.5
V
V
V
65
169
273
481
45
65
180
295
525
45
66
174
282
498
25
100
205
310
520
60
100
216
332
565
60
120
236
352
585
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.41
0.72
0.97
1.45
0.63
0.86
1.09
1.56
W
W
W
W
0.18
0.42
0.66
1.14
0.18
0.48
0.78
1.39
0.28
0.51
0.75
1.22
0.28
0.58
0.88
1.48
W
W
W
W
W
W
W
W
Data Device Corporation
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4
BU-65743/65843/65863/65864
AC-6/11-0
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
PARAMETER
CLOCK INPUT
PCI CLOCK INPUT FREQUENCY
1553 Clock Frequency
• Default Mode
• Option
• Option
• Option
•
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
•
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First Message
(for Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout
(Note 10)
• 18.5 nominal
•
22.5 nominal
•
50.5 nominal
•
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
THERMAL
80-Pin, Ceramic Flatpack/Gull Lead
Thermal Resistance, Junction-to-
Case, Hottest Die (θ
JC
) (Note 12)
MIN
TYP
MAX
33.3
16.0
12.0
10.0
20.0
-0.01
-0.10
-0.001
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
PARAMETER
THERMAL (CONT.)
324-Ball Plastic BGA
Thermal Resistance,Junction-to-Ball,
Hottest Die (θ
JB
)
ALL PACKAGES
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
-EXX
Storage Temperature
Soldering
Flat Pack/Gull Wing
Lead Temperature (soldering, 10 sec.)
324-ball BGA Package
The reflow profile detailed in IPC/
JEDEC J-STD-020 is applicable for
both leaded and lead-free products
PHYSICAL CHARACTERISTICS
80-Pin, Ceramic Flatpack/Gull Lead
Size, MAXIMUM
Micro-ACE-TE
Moisture Sensitivity Level
Electrostatic Discharge Sensitivity
Lead Toe-to-Toe Distance
80-Pin Gull Lead, MAXIMUM
Weight
324-ball Plastic BGA
Size, Maximum
Weight
MIN
TYP
MAX
UNITS
UNITS
MHz
MHz
MHz
MHz
MHz
12
-55
-40
0
-40
-65
+125
+85
+70
+100
+150
°C/W
°C
°C
°C
°C
°C
0.01
0.10
0.001
%
%
%
%
µs
-0.01
2.5
0.01
+300
+245
°C
°C
9.5
10.0
to
10.5
17.5
21.5
49.5
127
4
18.5
22.5
50.5
129.5
µs
µs
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
0.89 X 0.89 X 0.130
(22.6 x 22.6 x 3.3)
MSL-3
ESD Class 0
1.13
(28.7)
0.4
(10)
0.815 X 0.815 X 0.120
(20.7 x 20.7 x 3.05)
0.088
(2.5)
in.
(mm)
660.5
in.
(mm)
Oz.
(g)
in.
(mm)
Oz.
(g)
9
11
°C/W
TABLE 1 NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance and
Differential Capacitance specifications:
1.
Specifications include both transmitter and receiver (tied together internally).
2.
Impedance parameters are specified directly between pins TX/RX_A(B) and
TX/RX_A(B) of the PCI Mini-ACE Mark3/PCI Micro-ACE TE hybrid.
3.
It is assumed that all power and ground inputs to the hybrid are connected.
4.
The specifications are applicable for both unpowered and powered condi-
tions.
5.
The specifications assume a 2 volt rms balanced, differential, sinusoidal
input. The applicable frequency range is 75 kHz to 1 MHz.
6.
Minimum resistance and maximum capacitance parameters are guaranteed
over the operating range, but are not tested.
7.
Assumes a common mode voltage within the frequency range of dc to 2
MHz, applied to pins of the isolation transformer on the stub side (either
direct or transformer coupled), and referenced to hybrid ground. Transformer
must be a DDC recommended transformer or other transformer that provides
an equivalent minimum CMRR.
8.
Typical value for minimum intermessage gap time. Under software control,
this may be lengthened to 65,535 ms - message time, in increments of 1 µs.
If ENHANCED CPU ACCESS, bit 14 of Configuration Register #6, is set to
logic "1", then host accesses during BC Start-of-Message (SOM) and End-
of-Message (EOM) transfer sequences could have the effect of lengthening
the intermessage gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock cycles.
Since there are 7 internal transfers during SOM, and 5 during EOM, this
could theoretically lengthen the intermessage gap by up to 72 clock cycles;
i.e., up to 7.2 µs with a 10 MHz clock, 6.0 µs with a 12 MHz clock, 4.5 µs
with a 16 MHz clock, or 3.6 µs with a 20 MHz clock.
9.
For Enhanced BC mode, the typical value for intermessage gap time is
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
approximately 10 clock cycles longer than for the non-enhanced BC mode.
That is, an addition of 1.0 µs at 10 MHz, 833 ns at 12 MHz, 625 ns at 16
MHz, or 500 ns at 20 MHz.
Software programmable (4 options). Includes RT-to-RT Timeout (measured
mid-parity of transmit Command Word to mid-sync of transmitting RT Status
Word).
Measured from mid-parity crossing of Command Word to mid-sync crossing of
RT's Status Word.
θJC
is measured to the bottom of the case, and the numbers indicated are
preliminary
External 10 µF Tantalum and 0.1 µF capacitors should be located as close as
possible to Pin 10, and a 0.1 µF at pins 30, 51 & 69.
MIL-STD-1760 requires that the PCI Mini-ACE Mark3 produce a 20 Vp-p mini-
mum output on the stub connection.
Power dissipation specifications assume a transformer coupled configuration
with external dissipation (while transmitting) of 0.14 watts for the active isola-
tion transformer, 0.08 watts for the active bus coupling transformer, 0.45 watts
for each of the two bus isolation resistors and 0.15 watts for each of the two
bus termination resistors.
The 5V tolerant pins are RTAD0-5, RTAD_PAR, RTAD_LAT, TXINH_A/B,
SSFLAG*/EXT_TRIG, TAG_CLK, RTBOOT_L, CLK_SEL_0 and CLK_SEL_1.
Current drain and power dissipation specs are based upon a small sampling
of 3.3V transceivers and are subject to change.
Power dissipation is the input power minus the power delivered to the 1553
fault isolation resistors, the power delivered to the bus termination resistors
and the copper losses in the transceiver isolation transformer and the bus
coupling transformer.
The effective input capacitance as seen from the 1553 bus is reduced by the
square of the turns ratio of the coupling transformer.
Data Device Corporation
www.ddc-web.com
5
BU-65743/65843/65863/65864
AC-6/11-0
FPGA/CPLD
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