BDX18NR1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Discrete semiconductor> The transistor> BDX18NR1

BDX18NR1: DescriptionPower Bipolar Transistor, 15A I(C), 70V V(BR)CEO, 1-Element, PNP, Silicon, TO-204AA, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN; CategoryDiscrete semiconductor The transistor; File Size11KB，1 Pages; ManufacturerTT Electronics plc; Websitehttp://www.ttelectronics.com/; Environmental Compliance

Download Datasheet Parametric Compare View All

BDX18NR1 Overview

Power Bipolar Transistor, 15A I(C), 70V V(BR)CEO, 1-Element, PNP, Silicon, TO-204AA, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN

BDX18NR1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	TT Electronics plc
package instruction	FLANGE MOUNT, O-MBFM-P2
Reach Compliance Code	compliant
ECCN code	EAR99
Shell connection	COLLECTOR
Maximum collector current (IC)	15 A
Collector-emitter maximum voltage	70 V
Configuration	SINGLE
Minimum DC current gain (hFE)	20
JEDEC-95 code	TO-204AA
JESD-30 code	O-MBFM-P2
JESD-609 code	e1
Number of components	1
Number of terminals	2
Package body material	METAL
Package shape	ROUND
Package form	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	PNP
Certification status	Not Qualified
surface mount	NO
Terminal surface	TIN SILVER COPPER
Terminal form	PIN/PEG
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Transistor component materials	SILICON
Nominal transition frequency (fT)	0.8 MHz

Preview

Download Datasheet

View All

BDX18N

Dimensions in mm (inches).

25.15 (0.99)

26.67 (1.05)

10.67 (0.42)

11.18 (0.44)

1.52 (0.06)

3.43 (0.135)

6.35 (0.25)

9.15 (0.36)

Bipolar PNP Device in a

Hermetically sealed TO3

Metal Package.

38.61 (1.52)

39.12 (1.54)

0.97 (0.060)

1.10 (0.043)

29.9 (1.177)

30.4 (1.197)

22.23

(0.875)

max.

16.64 (0.655)

17.15 (0.675)

Bipolar PNP Device.

CEO

= 70V

(case)

3.84 (0.151)

4.09 (0.161)

7.92 (0.312)

12.70 (0.50)

= 15A

All Semelab hermetically sealed products

can be processed in accordance with the

requirements of BS, CECC and JAN,

JANTX, JANTXV and JANS specifications.

TO3 (TO204AA)

PINOUTS

1 – Base

2 – Emitter

Case - Collector

Parameter

CEO

C(CONT)

Test Conditions

Min.

Typ.

Max.

Units

@ 4/4 (V

/ I

)

0.8M

117

* Maximum Working Voltage

This is a shortform datasheet. For a full datasheet please contact

sales@semelab.co.uk.

Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed

to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use.

Semelab plc.

Telephone +44(0)1455 556565. Fax +44(0)1455 552612.

E-mail:

sales@semelab.co.uk

Website:

http://www.semelab.co.uk

Generated

31-Jul-02

BDX18NR1 Related Products

	BDX18NR1	BDX18N
Description	Power Bipolar Transistor, 15A I(C), 70V V(BR)CEO, 1-Element, PNP, Silicon, TO-204AA, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN	Power Bipolar Transistor, 15A I(C), 70V V(BR)CEO, 1-Element, PNP, Silicon, TO-204AA, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN
Is it Rohs certified?	conform to	incompatible
Maker	TT Electronics plc	TT Electronics plc
package instruction	FLANGE MOUNT, O-MBFM-P2	FLANGE MOUNT, O-MBFM-P2
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Shell connection	COLLECTOR	COLLECTOR
Maximum collector current (IC)	15 A	15 A
Collector-emitter maximum voltage	70 V	70 V
Configuration	SINGLE	SINGLE
Minimum DC current gain (hFE)	20	20
JEDEC-95 code	TO-204AA	TO-204AA
JESD-30 code	O-MBFM-P2	O-MBFM-P2
Number of components	1	1
Number of terminals	2	2
Package body material	METAL	METAL
Package shape	ROUND	ROUND
Package form	FLANGE MOUNT	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Polarity/channel type	PNP	PNP
Certification status	Not Qualified	Not Qualified
surface mount	NO	NO
Terminal form	PIN/PEG	PIN/PEG
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
Transistor component materials	SILICON	SILICON
Nominal transition frequency (fT)	0.8 MHz	0.8 MHz

Recommended Resources

Linear infrared anti-theft alarm circuit

Transformers, resistors, capacitors, and direct-coupled amplifiers

Transformerless switching power supply circuit diagram

Clever use of KD-28 to make a single-chip radio circuit diagram

Internal structure of UC3906

Three-phase exhaust fan power-saving automatic control circuit

Application of ultrasonic sensors in autonomous driving environment perception: With the rapid development of science and technology, ultrasonic waves will be used more and more widely in sensors. In the industrial revolutions of human civilization, sensor technology has always p...; sensor123 Automotive Electronics

Show off the MSP430 LaunchPad development board exchanged for E coins: [align=left][font=宋体]Figure[/font]1 [font=宋体]Outer packaging[/font][/align][align=left][font=宋体] [/font][/align] [align=left][font=宋体]Figure[/font]2 [font=宋体]Internal components[/font][/align][font=宋体...; jinglixixi Talking

【Original】Cyclone III FPGA development board related experimental routines continue to update: Software Quqartus10.0SP1 Hardware FPGA gift development board A3 miniFirst experiment with a Nios2 to read the contents of the SD card. The file system is fat16. It does not support high-speed cards a...; giftFPGA FPGA/CPLD

Red Series (I): Take a sneak peek, I’ve sorted them out and will show them to you one by one....; babbage Automotive Electronics

Principle and structure of positive displacement flowmeter: Volumetric flow measurement uses a fixed small volume to repeatedly measure the volume of fluid passing through the flowmeter. Therefore, there must be a space inside the volumetric flowmeter that con...; totopper Industrial Control Electronics

Help: DS-5 naked running comes with hello_world compilation error: Hello everyone, I recently want to use CycloneV SOC FPGA to run some simple routines to familiarize myself with SOC development. When running the routine that comes with DS-5: Altera-SoCFPGA-HelloWorl...; hunansunjianjun FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components