PAL20R8DJC datasheet, PDF - EEWORLD Datasheet

PAL20R8DJC: DescriptionOT PLD, 10ns, CDIP24, CERAMIC, DIP-24; CategoryProgrammable logic devices Programmable logic; File Size681KB，18 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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PAL20R8DJC Overview

OT PLD, 10ns, CDIP24, CERAMIC, DIP-24

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Texas Instruments
Parts packaging code	DIP
package instruction	DIP, DIP24,.3
Contacts	24
Reach Compliance Code	unknown
Other features	POWER-UP RESET; REGISTER PRELOAD
Architecture	PAL-TYPE
maximum clock frequency	55.5 MHz
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
Dedicated input times	12
Number of I/O lines
Number of entries	12
Output times	8
Number of product terms	64
Number of terminals	24
Maximum operating temperature	75 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 0 I/O
Output function	REGISTERED
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	10 ns
Certification status	Not Qualified
Maximum seat height	5.715 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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