FUJITSU SEMICONDUCTOR
DATA SHEET
DS05–20816–2E
FLASH MEMORY
CMOS
8M (1M
×
8/512K
×
16)
MBM29F800T/MBM29F800B
s
DISTINCTIVE CHARACTERISTICS
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard word-wide pinouts
48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance
90 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T=Top sector
B=Bottom sector
• Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for cletection of program or erase cycle completion
• Low power consumption
20 mA typical active read current for Byte Mode
28 mA typical active read current for Word Mode
30 mA typical write/erase current
25
µA
typical standby current
• Low Vcc write inhibit
≤
3.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
(Continued)
Embedded Erase™and Embedded Program™ are trademarks of Advanced Micro Devices, Inc.
MBM29F800T/800B
(Continued)
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
Hardware method temporarily enables any combination of sectors from write on erase operations
s
PACKAGE
Marking side
↓
Marking side
↓
↑
Marking side
(FPT-48P-M19)
48-pin TSOP
(FPT-48P-M20)
(FPT-44P-M16)
44-pin SOP
2
MBM29F800T/800B
s
GENERAL DESCRIPTION
The MBM29F800T/B is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of
16 bits each. The MBM29F800T/B is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed
to be programmed in-system with the standard system 5.0 V V
CC
supply. A 12.0 V V
PP
is not required for write or
erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F800T/B offers access times 90 ns and 120 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus contention the device has separate chip enable (
CE
), write enable
(
WE
), and output enable (
OE
) controls.
The MBM29F800T/B is pin and command set compatible with JEDEC standard. Commands are written to the
command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the device is similar to reading from
12.0 V Flash or EPROM devices.
The MBM29F800T/B is programmed by executing the program command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in less than one second. Erase is accom-
plished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
Any individual sector is typically erased and verified in 1.0 seconds (if already completely preprogrammed.)
This device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F800T/B is erased when shipped from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically inhibits
write operations on the loss of power. The end of program or erase is detected by
Data
Polling of DQ
7
, by the
Toggle Bit feature on DQ
6
, or the RY/
BY
output pin. Once the end of a program or erase cycle has been completed,
the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels of
quality, reliability, and cost effectiveness. The MBM29F800T/B memory electrically erases the entire chip or all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at
a time using the EPROM programming mechanism of hot electron injection.
3
MBM29F800T/800B
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
• Individual-sector, multiple-sector, or bulk-erase capability.
• Individual or multiple-sector protection is user definable.
FFFFFh
16K byte
FBFFFh
8K byte
F9FFFh
8K byte
F7FFFh
32K byte
EFFFFh
64K byte
DFFFFh
64K byte
CFFFFh
64K byte
BFFFFh
64K byte
AFFFFh
64K byte
9FFFFh
64K byte
8FFFFh
64K byte
7FFFFh
64K byte
6FFFFh
64K byte
5FFFFh
64K byte
4FFFFh
64K byte
3FFFFh
64K byte
2FFFFh
64K byte
1FFFFh
64K byte
0FFFFh
64K byte
00000h
MBM29F800T Sector Architecture
MBM29F800B Sector Architecture
16K byte
8K byte
8K byte
32K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
FFFFFh
EFFFFh
DFFFFh
CFFFFh
BFFFFh
AFFFFh
9FFFFh
8FFFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
07FFFh
05FFFh
03FFFh
00000h
4
MBM29F800T/800B
s
PRODUCT SELECTOR GUIDE
Part No
V
CC
= 5.0V±5%
Ordering Part No
V
CC
= 5.0V±10%
Max Access Time (ns)
CE Access (ns)
OE Access (ns)
—
90
90
60
– 12
120
120
60
– 90
MBM29F800T/MBM29F800B
—
s
BLOCK DIAGRAM
RY/BY
Buffer
V
CC
V
SS
DQ
0
to DQ
15
RY/BY
Erase Voltage
Generator
Input/Output
Buffers
WE
BYTE
RESET
State
Control
Command
Register
Program Voltage
Generator
CE
OE
Chip Enable
Output Enable
Logic
STB
Data Latch
STB
Y-Decoder
Y-Gating
V
CC
Detector
Timer
Address
Latch
X-Decoder
Cell Matrix
A
0
to A
18
A-1
5