PDM41258
256K Static RAM
64K x 4-Bit
Features
n
1
2
3
4
5
6
Description
The PDM41258 is a high-performance CMOS static
RAM organized as 65,536 x 4 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE goes LOW.
The PDM41258 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41258 comes in two versions,
the standard power version PDM41258SA and a low
power version the PDM41258LA. The two versions
are functionally the same and only differ in their
power consumption.
The PDM41258 is available in a 24-pin 300-mil plas-
tic SOJ for surface mount applications.
High speed access times
Com’l: 7, 8, 10, 12 and 15 ns
Ind’l: 8, 10, 12 and 15 ns
Low power operation (typical)
- PDM41258SA
Active: 400 mW
Standby: 150 mW
- PDM41258LA
Active: 350 mW
Standby: 25 mW
Single +5V (±10%) power supply
TTL compatible inputs and outputs
Packages
Plastic SOJ (300 mil) - SO
n
n
n
n
Functional Block Diagram
A
0
•
•
•
•
•
A
15
7
Decoder
•
•
•
•
•
•
Memory
Matrix
Addresses
8
9
10
11
I/O
0
I/O
1
I/O
2
I/O
3
• • • • •
Input
Data
Control
Column I/O
CE
WE
12
1
Rev. 2.2 - 4/27/98
PDM41258
Pin Configuration
SOJ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
Vss
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A15
A14
A13
A12
A11
A10
I/O3
I/O2
I/O1
I/O0
WE
Pin Description
Name
A15-A0
I/O3-I/O0
WE
CE
V
CC
V
SS
Description
Address Inputs
Data Inputs and Outputs
Write Enable Input
Chip Enable Input
Power (+5V)
Ground
Truth Table
WE
X
H
L
CE
H
L
L
I/O
Hi-Z
D
OUT
D
IN
MODE
Standby
Read
Write
NOTE:1.H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
T
TERM
T
BIAS
T
STG
P
T
I
OUT
T
j
Rating
Terminal Voltage with Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Maximum Junction Temperature
(2)
Com’l.
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
50
125
Ind.
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
50
145
Unit
°C
°C
°C
W
mA
°C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability
.2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
θ
ja
, where T
a
is the ambient tempera-
ture, P is average operating power and
θ
ja
the thermal resistance of the package. For
this product, use the following
θ
ja
value:
SOJ: 83
o
C/W
2
Rev. 2.2 - 4/27/98
PDM41258
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Industrial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
4.5
0
0
–40
Typ.
5.0
0
25
25
Max.
5.5
0
70
85
Unit
V
V
°C
°C
1
2
3
DC Electrical Characteristics
(1)
(V
CC
= 5.0V
±
10%)
PDM41258SA
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OL
= 10 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= MAX., V
IN
= V
SS
to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
= V
SS
to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
PDM41258LA
Min.
–5
–5
–0.5
(1)
2.2
—
—
2.4
Max.
5
5
0.8
6.0
0.4
0.5
—
Unit
µA
µA
V
V
V
V
V
4
5
6
7
NOTE: 1. V
IL
(min) = –3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-7
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max
I
SB1
Full Standby Current
CE
≥
V
CC
– 0.2V
f=0
V
CC
= Max
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
Power
SA
LA
Com’l.
210
190
-8
Com’l.
200
180
Ind.
210
190
-10
Com’l.
190
170
Ind.
200
180
-12
Com’l.
180
160
Ind.
190
170
-15
Com’l.
170
150
Ind.
180
160
Units
mA
mA
8
9
10
11
12
SA
LA
SA
LA
90
90
20
5
80
80
20
5
80
80
20
5
70
70
20
5
70
70
20
5
60
60
20
5
60
60
20
5
50
50
20
5
50
50
20
5
mA
mA
mA
mA
SHADED AREA = PRELIMINARY DATA
NOTE:All values are maximum guaranteed values.
Rev. 2.2 - 4/27/98
3
PDM41258
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
NOTE: 1.This parameter is determined by device characterization but is not production tested.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
3 ns
1.5V
1.5V
See Figures 1 and 2
+5V
480Ω
D
OUT
255Ω
30 pF
+5V
480Ω
D
OUT
255Ω
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
)
Delta tAA - nS
5
4
3
2
1
0
0
Typical Delta tAA vs Capacitive Loading
30
60
90
120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4
Rev. 2.2 - 4/27/98
PDM41258
Read Cycle No. 1
(1)
ADDR
t OH
t AA
DATA VALID
t RC
1
2
3
DOUT PREVIOUS DATA VALID
Read Cycle No. 2
(2)
t
RC
ADDR
4
t
HZCE
t
AA
t
ACE
CE
t
LZCE
5
t
HZOE
t
LZOE
D
OUT
DATA VALID
6
7
t
AOE
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(3, 4, 5)
8
-7
(6)
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
0
7
3
5
5
0
8
Min.
7
7
7
3
5
5
0
10
Max.
-8
(6)
Min.
8
8
8
3
5
10
0
12
Max.
-10
(6)
Min.
10
10
10
3
5
10
0
15
Max.
Min.
12
12
12
3
5
10
-12
Max.
Min.
15
15
15
-15
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
9
10
11
12
5
Chip disable to output in high Z
(3, 4, 5)
Chip enable to power up time
(4)
Chip disable to power down time
(4)
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
Rev. 2.2 - 4/27/98
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