PACSZ1284
IEEE 1284 Parallel Port
ESD/EMI/Termination
Network
Product Description
The PACSZ1284 combines EMI filtering, ESD protection, and
signal termination in a single QSOP package for parallel port
interfaces complying to the IEEE 1284 standard.
The PACSZ1284 provides a complete parallel port termination
solution. It integrates the equivalent of 60 discrete components,
making it ideal for space critical applications. The pins of the device
which connect to the parallel port are protected to
30
kV contact
discharge, well beyond Level 4 of the IEC 61000−4−2 specification.
All other pins are ESD−protected for contact discharges up to
8
kV
per IEC 61000−4−2.
There are two values available for pull−up resistor R1. For the
PACSZ1284−02, R1 = 2.2 kW; for the PACSZ1284−04, R1 = 4.7 kW.
The PACSZ1284 is housed in a 28−pin QSOP package and is
available with RoHS compliant lead−free finishing.
Features
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QSOP−28
QR SUFFIX
CASE 492AA
MARKING DIAGRAM
PACSZ1284 02QR
17 EMI Filters
17 ESD Protectors Yielding Protection to 30 kV Contact
Discharge, per IEC 61000−4−2 Specification
17 Terminators with Choice of Resistor Values
28−Pin QSOP Package
These Devices are Pb−Free and are RoHS Compliant
Applications
PACSZ1284 02QR
= Specific Device Code
PACSZ128404QR
PACSZ128404QR
= Specific Device Code
Parallel Ports of PCs, Printers, Peripherals, and Set−Top Boxes
ORDERING INFORMATION
Device
Package
Shipping
†
PACSZ1284−02QR QSOP−28 2500/Tape & Reel
(Pb−Free)
PACSZ1284−04QR QSOP−28 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2011
October, 2011
−
Rev. 4
1
Publication Order Number:
PACSZ1284/D
PACSZ1284
ELECTRICAL SCHEMATIC
PACSZ1284−02
R1 = 2.2 kW
R2 = 33
W
C = 150 pF
28
27
26
25
24
23
22 21
20
19
18
17
PACSZ1284−04
R1 = 4.7 kW
R2 = 33
W
C = 150 pF
16
15
R1
R1
R1
R1
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R1
R1
R2
R1
R1
R2
R1
R1
R2
R1
R2
R1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PACKAGE / PINOUT DIAGRAMS
CAP−FILTERED
CAP−FILTERED
SUPERCHIP SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
CAP−FILTERED
SUPERCHIP SIDE SERIES−TERMINATED
CAP−FILTERED
SUPERCHIP SIDE SERIES−TERMINATED
CAP−FILTERED
SUPERCHIP SIDE SERIES−TERMINATED
SUPERCHIP SIDE SERIES−TERMINATED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28−Pin QSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CAP−FILTERED
CAP−FILTERED
CONNECTOR SIDE SERIES−TERMINATED
CONNECTOR SIDE SERIES−TERMINATED
CONNECTOR SIDE SERIES−TERMINATED
CONNECTOR SIDE SERIES−TERMINATED
GND
CONNECTOR SIDE SERIES−TERMINATED
V
CC
CONNECTOR SIDE SERIES−TERMINATED
CONNECTOR SIDE SERIES−TERMINATED
CONNECTOR SIDE SERIES−TERMINATED
CONNECTOR SIDE SERIES−TERMINATED
CAP−FILTERED
Table 1. PIN DESCRIPTIONS
Leads
1, 2, 8, 10, 12, 15, 27, 28
3−7, 9, 11, 13, 14
16−19, 21, 23−26
20
22
Name
Capacitor−Filtered
Super I/O Chip Side Series−Terminated
Parallel Port
Connector Side Series−Terminated
V
CC
GND
Description
IEEE 1284 Signals which Require No Series Termination
IEEE 1284 Signals on the Super I/O Chip Side which Require
Series Termination
IEEE 1284 Signals on the Parallel Port Connector Side which
Require Series Termination
Supply Rail for the Device
Ground Reference for the Device
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2
PACSZ1284
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC
Voltage
Input Voltage Range, No Clamping
Storage Temperature Range
Power Dissipation per Resistor
Package Power Dissipation
Rating
5.5
−0.4
to 5.5
−40
to +150
0.1
1.0
Units
V
V
C
W
W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
V
CC
Voltage
Operating Temperature
Rating
5.0
−40
to +85
Units
V
C
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
Symbol
TOL
R
TOL
C
I
LEAK
V
ESDi
Parameter
Absolute Resistance Tolerance
Absolute Capacitance Tolerance
Leakage Current to GND
ESD Protection, Input Pins
Conditions
Measured at T
A
= 25C
Measured at 1 MHz, 2.5 VDC,
T
A
= 25C
Measured at 5.0 VDC, T
A
= 25C
Pins 3, 4, 5, 6, 7, 9, 11, 13, & 14,
per IEC 61000−4−2 Specification
(Notes 1 and 2)
Pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19,
21, 23, 24, 25, 26, 27, & 28,
per IEC 61000−4−2 Specification
(Notes 1 and 3)
ESD Applied to Connector Pin,
Measured at Corresponding Input Pin;
+8 kV Discharge, Human Body Model
(Note 1)
ESD Applied to Connector Pin,
Measured at Corresponding Input Pin;
−8
kV Discharge, Human Body Model
(Note 1)
1. ESD voltage applied between Input/Connector pins and ground, one pin at a time.
2. Pins 3−7, 9, 11, 13, and 14 typically connect to the I/O pins of a Super I/O chip.
3. Pins 1, 2, 8, 10, 12, 15−19, 21, and 23−28 typically connect to the Parallel Port connector.
8
1
Min
Typ
Max
20
20
10
Units
%
%
mA
kV
V
ESD
ESD Protection, Connector Pins
30
kV
V
CLAMP
Clamping Voltage under ESD Discharge
8.3
V
−2.7
V
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PACSZ1284
PERFORMANCE INFORMATION
Filter Capacitors
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 lines. Basic filtering is provided
through the presence of a capacitor on all signal lines. The filter capacitor is the junction capacitance of an ESD diode. The
typical capacitance at a reverse voltage of 2.5 V is 150 pF. This diode capacitance is somewhat voltage dependent. See Figure 1.
Figure 1. Diode Capacitance vs. Reverse Voltage
The higher speed Data and Strobe lines (9 in total) require an additional series resistor termination for proper operation, while
the eight (8) Status lines do not. See Table 5.
Filter Insertion Loss
Figure 2 shows the typical Insertion Loss graphs of the PACSZ1284 for Data and Strobe signals. The curves are dependent
on the physical location of the filter elements with respect to the ground terminal of this device. These graphs are measured
in a 50
W
environment on a Hewlett Packard HP 8753C Analyzer. The signal source is introduced at the resistor input and the
output is measured at the corresponding protection diode. The actual pins measured are labeled in the Figure 2 graph.
Figure 2. Typical Filter Insertion Loss
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PACSZ1284
APPLICATION INFORMATION
Termination Considerations
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 signal lines. Control and Status
lines (8 in total) only require a pull−up resistor and a filter capacitor. The Data lines and Strobe also require a series termination
resistor in addition to the pull−up resistors and filter capacitors. See Table 5, in conjunction with the schematic diagram on
page 2.
Table 5. IEEE 1284 TERMINATION REQUIREMENTS
Signal Termination Requirements
Signal Name
Data1
−
Data8
Strobe
Init
AutoFeedXT
Selectin
ACK
Busy
Paper Empty
Select
Fault
Series Termination
Yes
Yes
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Interfacing to IEEE 1284 Connectors
IEEE 1284 defines three interface connectors:
1284 A is a 25−pin DB series connector which is the de facto PC standard for the host connection
1284 B is a 36−pin, 0.085 inch centerline connector used on the peripheral device
1284 C is a new 36−pin, 0.050 inch centerline connector which can be used for both host and peripheral
Figure 3A shows a possible hook−up between the 1284−A connector on a PC motherboard and the PACSZ1284, illustrating
how the pin configuration of the PACSZ1284 allows for easy interconnect between the two. The dotted I/O signals of the
PACSZ1284 will typically be connected to a Super I/O chip on the motherboard.
Figure 3B shows a possible hook−up between the 1284−B connector on a peripheral and the PACSZ1284
Figure 3C shows a possible hook−up between the 1284−C connector and the PACSZ1284.
Figure 3. Example Connections of IEEE 1284 Connectors with PACSZ1284
Table 6 provides the IEEE 1284 signal assignments for the three connectors, and example PACSZ1284 pin connections.
When connecting a 1284−A host to a 1284−B peripheral, the “Peripheral Logic High” signal is not used. Similarly, when
a 1284−A host is connected to a 1284−C peripheral, the “Peripheral Logic High” and “Host Logic High” are not used. These
two signals are optionally used to detect a “Power Off” or “Cable Disconnect” state for host and peripheral, respectively.
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