Crystal connection or external reference frequency input. It can be connected
to a 25MHz Fundamental mode crystal.
Connection to crystal. If using an external reference clock, this pin must be
left unconnected.
25MHz Reference Clock output.
125MHz Clock Output.
125MHz Clock Output.
127MHz Clock Output.
125MHz Clock Output.
Connect to ground.
No connection.
No connection.
Connect to +3.3V.
No connection.
Output Enable bit. When this pin is made HIGH, all clocks are enabled.
Tri-states all clocks when this pin is LOW
.
Power
Input
Rev. 1 | Page 2 of 6 | www.onsemi.com
PCS1P2860A
Absolute Maximum Ratings
Symbol
VDD
V
IN
T
STG
T
s
T
J
T
DV
Parameter
Rating
-0.5 to +4.6
-0.5 to VDD+0.3
-65 to +150
260
125
2
Unit
V
°
C
°
C
°
C
KV
Power Supply Voltage relative to Ground
Input Voltage relative to Ground (Input Pins)
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
VDD / AVDD Operating Voltage
T
A
C
L
C
IN
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
5
Description
Min
3.135
0
Typ
3.3
Max
3.465
70
15
Unit
V
°
C
pF
pF
DC Electrical Characteristics
Symbol
Parameter
VDD / AVDD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OZ
I
CC
I
DD
Z
OUT
Operating Voltage
Input High Voltage
Input Low Voltage
Input HIGH current
Input LOW current
Output High Voltage
Output Low Voltage
Output Leakage Current
Static Current
Dynamic Current
Nominal output impedance
Conditions
Min
3.135
2.2
GND-0.3
Typ
3.3
Max
3.465
VDD+0.3
1.0
30
50
Units
V
V
V
µA
µA
V
V
µA
mA
mA
VIN = VDD
VIN = GND
VDD = 3.135, I
OH
= -12mA
VDD = 3.135, I
OL
= 12mA
Three-state outputs
CLKIN and SHUTDOWNB
Pins pulled low
No Load, All Clocks on
2.4
0.4
10
5.5
35
30
Rev. 1 | Page 3 of 6 | www.onsemi.com
PCS1P2860A
AC Electrical Characteristics
Symbol
CLKIN / XIN
CLK OUT
t
LH
t
HL
1
1
1
Parameter
Input Frequency
Pin 6
Output Frequency
Pin 1,7,8,10
Pin 9
Rising edge slew rate (Measured from 20% to 80%)
Falling edge slew rate (Measured from 80% to 20%)
Peak-to-peak Period Jitter @ VDD/2
Synthesis Error (Output Frequency)
Output Duty Cycle @ VDD/2
PLL Lock Time from Power-Up
Min
Typ
25
25
125
127
Max
Unit
MHz
MHz
V/nS
V/nS
pS
ppm
1.1
1.3
1.7
2
300
0
T
PJ
t
D
1
45
50
55
3
%
mS
t
LOCK
NOTE: 1. CL= 15pF for outputs < 100MHz; CL = 10pF for outputs > 100MHz;
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal
Nominal frequency
Frequency tolerance
Operating temperature range
Storage temperature
Load capacitance(C
P
)
Shunt capacitance
ESR
25MHz
± 50 ppm or better at 25°
C
-25° to +85°
C
C
-40° to +85°
C
C
18pF
7pF maximum
25
Ω
Note: Note: C
L
is Load Capacitance and Rx is used to prevent oscillations at overtone frequency of the Fundamental frequency.
Typical Crystal Interface Circuit
R
Crystal
Rx
C
L
C
L
C
L
= 2*(C
P
– C
S
),
Where C
P
= Load capacitance of crystal
C
S
= Stray capacitance due to C
IN,
PCB, Trace etc.
Rev. 1 | Page 4 of 6 | www.onsemi.com
PCS1P2860A
Package Information
16-lead Thin Shrunk Small Outline Package (4.40-MM Body)
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