DAC1408D650
Dual 14-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
Rev. 02 — 11 August 2010
Preliminary data sheet
1. General description
The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1408D650 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted from baseband to IF.
The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1408D650 also includes a 2×, 4× or 8× clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full scale current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1408D650 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode. It guarantees a maximum skew of one output clock period between two
devices.
2. Features and benefits
Dual 14-bit resolution
650 Msps maximum update rate
Selectable 2×, 4× or 8× interpolation
filters
Input data rate up to 312.5 Msps
Very low noise cap free integrated PLL
32-bit programmable NCO frequency
Four JESD204A serial input lanes
1.8 V and 3.3 V power supplies
LVDS compatible clock inputs
IMD3: 76 dBc; f
s
= 640 Msps;
f
o
= 140 MHz
ACPR: 71 dBc; two carriers WCDMA;
f
s
= 640 Msps; f
o
= 133 MHz
Typical 1.24 W power dissipation at 4×
interpolation, PLL off and 640 Msps
Power-down mode and Sleep modes
Differential scalable output current from
1.6 mA to 22 mA
On-chip 1.25 V reference
External analog offset control
(10-bit auxiliary DACs)
Internal digital offset control
Inverse (sin x) / x function
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
Fully compatible SPI port
Industrial temperature range from
−40 °C
to +85
°C
Integrated PLL can be bypassed
Embedded complex modulator
Two’s complement or binary offset data
format
LMF = 421 or LMF = 211 support
Differential CML receiver with
embedded termination
Synchronization of multiple DAC
devices outputs
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point to point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1.
Ordering information
Package
Name
DAC1408D650HN/C1
HVQFN64
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; SOT804-3
64 terminals; body 9
×
9
×
0.85 mm; exposed die pad
Type number
DAC1408D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 — 11 August 2010
2 of 98
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5. Block diagram
SDIO
CSB
SCLK
DAC1408D650
FRAME ASSEMBLY
INTER LANE ALIGNMENT
Preliminary data sheet
NCO
32 bits frequency setting
16 bits phase adjustment
10 BITS
OFFSET
CONTROL
AUX.
DAC
AUXAN
AUXAP
cos
sin
10 BITS
GAIN
CONTROL
FIR 1
I DAC
IOUTAN
X
Sin X
+
Σ
FIR 2
FIR 3
IOUTAP
×
2
×
2
×
2
DACFSADJ
OFFSET
CONTROL
GAPOUT
SDO
NXP Semiconductors
SPI CONTROL REGISTERS
SYNC_OUTP
SYNC_OUTN
DIGITAL LAYER
PROCESSING
JESD204A
VIN_P0
L0
VIN_N0
LANE
PROC
VIN_P1
L1
VIN_N1
LANE
PROC
DAC1408D
VIN_P2
FIR 1
FIR 2
FIR 3
SINGLE
SIDE
BAND
MODULATOR
REF.
BANDGAP
AND
BIASING
L2
VIN_N2
LANE
PROC
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 August 2010
×
2
×
2
×
2
X
Sin X
+
Σ
MULTI-DAC
SYNCHRONISATION
RESET_N
MDS_OUTP
MDS_OUTN
VIN_P3
IOUTBP
Q DAC
IOUTBN
10 BITS
GAIN
CONTROL
L3
VIN_N3
LANE
PROC
CLOCK GENERATOR UNIT
AUX.
DAC
AUXBP
AUXBN
10 BITS
OFFSET
CONTROL
CLK_INP
CLK_INN
001aal068
DAC1408D650
© NXP B.V. 2010. All rights reserved.
Fig 1.
Block diagram
3 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
6. Pinning information
6.1 Pinning
50 SYNC_OUTN
51 SYNC_OUTP
59 V
DDD(1v8)
54 V
DDD(1v8)
terminal 1
index area
SDO
SDIO
SCLK
V
DDD(1v8)
SCS_N
RESET_N
n.c.
VIRES
GAPOUT
1
2
3
4
5
6
7
8
9
49 V
DDD(1v8)
48 n.c.
47 V
DDD(1v8)
46 MDS_N
45 MDS_P
44 V
DDA(1v8)
43 AGND
42 CLKINN
41 CLKINP
40 AGND
39 V
DDA(1v8)
38 V
DDA(1v8)
37 AGND
36 AUXAN
35 AUXAP
34 V
DDA(3v3)
33 AGND
V
DDA(1v8)
32
005aaa150
61 VIN_N3
57 VIN_N2
DAC1408D
HVQFN64
V
DDA(1v8)
10
V
DDA(1v8)
11
AGND 12
AUXBN 13
AUXBP 14
V
DDA(3v3)
15
AGND 16
V
DDA(1v8)
17
AGND 18
V
DDA(1v8)
19
V
DDA(1v8)
20
AGND 21
IOUTBN 22
IOUTBP 23
AGND 24
AGND 25
IOUTAP 26
IOUTAN 27
AGND 28
V
DDA(1v8)
29
V
DDA(1v8)
30
AGND 31
Transparent top view
Fig 2.
Pin configuration
6.2 Pin description
Table 2.
Symbol
SDO
SDIO
SCLK
V
DDD(1V8)
SCS_N
RESET_N
n.c.
VIRES
GAPOUT
V
DDA(1V8)
V
DDA(1V8)
DAC1408D650
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
Type
[1]
O
I/O
I
P
I
I
-
I/O
I/O
P
P
Description
SPI data output
SPI data input/output
SPI clock
digital supply voltage 1.8 V
SPI chip select (active LOW)
general reset (active LOW)
not connected
DAC biasing resistor
bandgap input/output voltage
analog supply voltage 1.8 V
analog supply voltage 1.8 V
© NXP B.V. 2010. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 02 — 11 August 2010
52 VIN_N0
60 VIN_P3
58 VIN_P2
55 VIN_P1
53 VIN_P0
56 VIN-N1
64 JTAG
63 n.c.
62 n.c.
4 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
Pin description
…continued
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Type
[1]
G
O
O
P
G
P
G
P
P
G
O
O
G
G
O
O
G
P
P
G
P
G
P
O
O
G
P
P
G
I
I
G
P
I/O
I/O
P
-
P
O
O
Description
analog ground
complementary auxiliary DAC B output
auxiliary DAC B output
analog supply voltage 3.3 V
analog ground
analog supply voltage 1.8 V
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
complementary DAC B output current
DAC B output current
analog ground
analog ground
DAC A output current
complementary DAC A output current
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
analog supply voltage 1.8 V
analog ground
analog supply voltage 3.3 V
auxiliary DAC A output current
complementary auxiliary DAC A output current
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
clock input
complementary clock input
analog ground
analog supply voltage 1.8 V
multi-devices synchronization
complementary multi-devices synchronization
digital supply voltage 1.8 V
not connected
digital supply voltage 1.8 V
synchronization request to transmitter, complementary
output
synchronization request to transmitter
© NXP B.V. 2010. All rights reserved.
Table 2.
Symbol
AGND
AUXBN
AUXBP
V
DDA(3V3)
AGND
V
DDA(1V8)
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
IOUTBN
IOUTBP
AGND
AGND
IOUTAP
IOUTAN
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
V
DDA(1V8)
AGND
V
DDA(3V3)
AUXAP
AUXAN
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
CLKINP
CLKINN
AGND
V
DDA(1V8)
MDS_P
MDS_N
V
DDD(1V8)
n.c.
V
DDD(1V8)
SYNC_OUTN
SYNC_OUTP
DAC1408D650
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 02 — 11 August 2010
5 of 98
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