SCG2000iG
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The Connor-Winfield SCG2000iG provides
high precision phase lock loop frequency
translation for telecommunication applications
that require a temperature range of -40°C to
85°C.
SCG2000iG is well suited for use in line
cards, service termination cards and similar
functions to provide reliable reference, phase
locked, synchronization and low phase gain
for TDM, PDH, SONET and SDH network
equipment. The SCG2000iG provides a jitter
filtered, wander following, output signal
synchronized to a superior Stratum or peer
input reference signal. This product is also
compliant with all required ROHS
specifications.
Features
•
Industrial Temperature
Range
•
3.3V High Precision
PLL
•
Tri-State Capability
•
Active Alarms
•
Guaranteed Free Run
(20ppm for 19.44MHz
output, 25ppm for
65.536MHz and 30ppm
for 125.0 MHz)
•
1 Sec. Acquisition Time
•
ROHS Compliant
Bulletin
Page
Revision
Date
Issued By
SG130
1 of 16
P00
12 JULY 06
MBATTS
General Description
The SCG2000iG provides high precision phase lock loop
frequency translation for telecommunication applications. The
SCG2000iG generates a CMOS output from an intrinsically low
jitter, voltage controlled crystal oscillator. while providing a jitter
attenuated, internal reference that is connected to a Reference
Output pin.
SCG2000iG is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH, SONET
and SDH network equipment . The SCG2000iG provides a low
phase gain (<0.2dB), jitter filtered, wander following output signal
synchronized to a superior Stratum or peer input reference
signal.
The SCG2000iG include the following features: Free Run, Tri-
state and alarm outputs for Loss-of-Reference, (LOR), Loss-of-
Lock, (LOL). During the LOR alarm, the SCG2000iG will also
enter a Free Run state which will guarantee a 20 ppm accurate
output with the 19.44 MHz model, 25ppm accurate with the
65.536 MHz and 30 ppm accurate output with the 125.0
MHz model. Additionally the Free Run mode may be
entered manually by asserting a high signal to the Free Run
Enable pin. The outputs, except the oscillator output, may
be put into the tri-state high impedance condition for
external testing purposes by asserting a high signal to the
Tri-State Enable pin.
The SCG2000iG operates at 3.3 Volts and typically
draws less than 100 mA. All models have an acquisition
time of approximately 1.0 second and can be used in
applications that require temperature rating of -40° to
85° C. All models have a 33Ω resistor in series with the
oscillator output. The SCG2000iG maximum package
dimensions are .78” x .83” x .35” on a six layer FR4 board
with surface mount pins. Parts are assembled using high
temperature solder to withstand surface mount reflow
process.
Functional Block Diagram
Figure 1
Tri-State Enable
(Pin 10)
10 kΩ
LOL Alarm Output
(Pin 7)
ALARM
DETECTION
Free Run Enable
(Pin 5)
2.2 kΩ
LOR Alarm Output
(Pin 6)
Reference Input
(Pin 8)
DIVIDER
27
Ω
DPFD
ANALOG
FILTER
FREE RUN
CONTROL
VCXO
33
Ω
Oscillator Output
(Pin 9)
DIVIDER
Input Freq. Select A
(Pin 14)
10 kΩ
33
Ω
Reference Output
(Pin 1)
Input Freq. Select B
(Pin 13)
10 kΩ
Model Comparison Table
Table 1
Model
Input
Ref Freq
Max
Duty
Cycle
40/60
45/55
40/60
40/60
45/55
40/60
40/60
Reference Output
(Pin #1)
= Input Ref Freq.
= Input Ref Freq.
8 kHz
19.44 MHz
= Input Ref Freq.
19.44 MHz
51.84 MHz, 77.76 MHz
Oscillator Output
(Pin #9)
1.544 MHz to 125.0 MHz
19.44 MHZ, 65.536 MHz,
125.0 MHz
19.44 MHz
77.76 MHz
1.544 MHz to 125.0 MHz
77.76 MHz
51.84 MHz, 77.76 MHz
Ref Output = Osc Output
Tight Duty Cycle
Notes
Basic Model
Industrial Temp. Range
SCG2000G 8-64 kHz
SCG2000iG 8-64 kHz
SCG2010G
19.44 MHz
SCG2020G
19.44 MHz
SCG2030G 8-64 kHz
SCG2050G 8-64 kHz
SCG2070G
19.44 MHz
*Features which differentiate a model from the base model (SCG2000G) are highlighted in boldface color and in the notes column.
Preliminary Data Sheet #:
SG130
Page
2
of
16
Rev:
P00
Date:
7/12/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Pin Description
Table 2
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Connection
Reference Output
TCK
TMS
Ground
Free Run Enable/TDI
Loss of Reference (LOR)
Loss of Lock (LOL)
Reference Input
Oscillator Output
Tri-State enable
Vcc
TDO
Input Freq. Select B
Input Freq. Select A
Description
Output frequency is dependent on SCG model
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Ground
Free Run enable pin. 1 = Free Run. Input is pulled to GND
Alarm indicator. 1 = The reference has been lost.
Alarm indicator. 1 = Phase lock has been lost
Input reference frequency
Output frequency is dependent on SCG model
Tri State control for all outputs except Oscillator Output. 1 = Hi-Z, 0 = normal.
Input is pulled to GND.
3.3V Supply Voltage.
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Control pin B used to select input frequency. Input is pulled to GND.
Control pin A used to select input frequency. Input is pulled to GND.
Pin Out Diagram
Figure 2
Reference Output
TCK
TMS
GND
Free Run Enable/TDI
Loss of Reference (LOR)
Loss of Lock (LOL)
Pin 1
Pin 14
Input Freq. Select a
Input Freq. Select B
TDO
Top View
VCC
Tri-State Enable
Oscillator Output
Pin 7
Pin 8
Reference Input
Preliminary Data Sheet #:
SG130
© Copyright 2006 The Connor-Winfield Corp.
Page
3
of
16
Rev:
P00
Date:
7/12/06
All Rights Reserved
Specifications subject to change without notice
Table 3
Symbol
Vcc
V1
Ts
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Absolute Maximum Rating
Minimum
-0.5
-0.5
-65
Nominal
Maximum
4
5.5
150
Units
Volts
Volts
deg. C
Notes
Table 4
Parameter
Voltage
Current
Temperature Range
Input Jitter Tolerance
(Input Jitter Frequencies > 10 Hz)
Specifications
Specifications
3.3V ±5%
<100 mA Typical
-40° to 85°C
≥31.25us
Typical
<15 Hz (8 Hz Typical)
Notes
1.0
Jitter Bandwidth
Typical Acquisition Time Data (SCG2000iG-019.44M & SCG2000iG-125.00M)
Acquisition from a cold power-up:
Phase lock within 1 UI:
~ 35 sec.
Phase lock settled:
~ 160 sec.
Alarm time:
< 1 sec.
Acquisition from Free Run:
Phase lock within 1 UI:
~ 35 sec.
Phase lock settled:
~ 160 sec,
Alarm time:
Typically no alarm
Frequency lock with a 20PPM reference frequency step: Typically <1 sec.
Typical Acquisition Time Data (SCG2000iG-65.536M)
Acquisition from a cold power-up:
Phase lock within 1 UI:
~ 4 sec.
Phase lock settled:
~ 60 sec.
Alarm time:
< 1 sec.
Acquisition from Free Run:
Phase lock within 1 UI:
~ 4 sec.
Phase lock settled:
~ 60 sec.
Alarm time:
Typically no alarm
Frequency lock with a 20PPM reference frequency step: Typically <0.5 sec.
Output Duty Cycle
45/55% Min/Max @ 50% Level
±32 ppm Minimum
Capture/Pull-in Range (SCG2000iG-65.536M)
±50 ppm Minimum
Output Rise and Fall Time (SCG2000iG-019.44M & SCG2000iG-125.00M)
3 ns @ 20% to 80% output level
Output Rise and Fall Time (SCG2000iG-65.536M)
1ns Typ. (1.5ns Max.) @ 20% to 80% output level
Output Load (SCG2000iG-019.44M & SCG2000iG-125.00M)
30 pF
Output Load (SCG2000iG-65.536M)
7.5 pF Max.
Capture/Pull-in Range (SCG2000iG-019.44M & SCG2000iG-125.00M)
Preliminary Data Sheet #:
SG130
Page
4
of
16
Rev:
P00
Date:
7/12/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Specifications (Continued)
Alarms
Free Run Accuracy
LOR, LOL Status on seperate outputs
±20 ppm (19.44 MHz output)
±25 ppm (65.536 MHz output)
±30 ppm (125.0 MHz output)
Fr4 SM 0.78" x .83" x 0.35" (maximum)
60 ps Typical @60s
750 ps Typical @60s
± 35 ns Maximum
± 18 ns Maximum
± 33 ns Maximum
2.0
Package
TDEV
MTIE
Static Offset
Dynamic Offset (25°C - 85°C)
(-40°C - 85°C)
NOTES:
Reference Output/Oscillator Output Offset
≤
8 ns
1.0: Requires external regulation
2.0: Offset between Reference Input and Reference Output @ room temp.
Input And Output Characteristics
Table 5
Symbol
V
IH
V
IL
T
IO
C
O
V
HO
V
IO
T
IR
Parameter
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
Output Capacitance
High Level Output Voltage l
oH
= -4mA
Low Level Output Voltage l
oL
= 8mA
Input Reference Signal Pulse Width
30
2.4
0.4
nS
Minimum
2
0
Nominal
Maximum
5.5
0.8
10
10
Units
V
V
nS
pF
Vcc Min.
Vcc Max.
Notes
Output Jitter Specifications
Table 6
Jitter BW 10 Hz - 20 MHz
Frequency (MHz)
19.44
65.536
125.0
pS (RMS)
10 Typ.
10 Typ.
10 Typ.
m UI
0.194 Typ.
0.655 Typ.
1.250 Typ.
SONET Jitter BW 12 KHz - 20 MHz
pS (RMS)
1 Max., 0.5 Typ.
1 Max., 0.5 Typ.
1 Max., 0.5 Typ.
m UI
0.019 Max.
0.066 Max.
0.125 Max.
Output Programming
Table 7
Tristate
0
1
0
Free Run
0
X
1
Output
Locked to reference selected (default)
Hi-Z Tristate condition
Free run
Alarm Status
Table 8
LOL Output LOR Output
0
1
X
0
0
1
Alarm Output
No alarm
Loss-of-Lock
Loss-of-Reference
Preliminary Data Sheet #:
SG130
© Copyright 2006 The Connor-Winfield Corp.
Page
5
of
16
Rev:
P00
Date:
7/12/06
All Rights Reserved
Specifications subject to change without notice
Analogue and Mixed Signal
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