SCG3040
Synchronous Clock
Generator
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The SCG3040 is designed for use as a
reference input for OC-48 Framers and
SERDES. It generates less than 1 psRMS
jitter over the OC-48 bandwidth.
SCG3040 is well suited for use in line
cards, service termination cards and
similar functions to provide reliable
reference, phase locked, synchronization
for TDM, PDH, SONET, and SDH network
equipment. The SCG3040 provides a jitter
filtered, wander following output signal
synchronized to a superior Stratum or peer
input reference signal.
Features
•
3.3V High
Precision PLL
•
Two Differential
LVPECL Outputs.
155.52 MHz or
77.76 MHz
•
19.44 MHz CMOS
Input Reference
•
Reference Duty
Cycle Tolerant
•
Low Temperature
Reflow Surface
Mounting
Bulletin
Page
Revision
Date
Issued By
SG033
1 of 12
P02
22 NOV 04
MBatts
General Description
The SCG3040 is a mixed signal phase locked loop
generating 77.76 MHz or 155.52 MHz Dual LVPECL
outputs from an intrinsically low jitter voltage controlled
crystal oscillator. The SCG3040 is phase locked to an
external 19.44 MHz reference input. The SCG3040 is
ideal for applications using multiplication to obtain
higher SONET frequencies.
The package dimensions are 0.75" x 1.25" x .45" on
a 6 layer, designed impedance, FR4 board with
castellated pins. Parts are assembled using high
temperature solder to withstand surface mount reflow
processes. See Fig. 4 for the solder profile.
Functional Block Diagram
Figure 1
REF
Filter
Low
Jitter
VCXO
Divider
LVPECL
Driver
Q1
QN1
Q2
QN2
Absolute Maximum Rating
Table 1
Symbol
V
CC
V
I
T
S
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Minimum
-0.5
-0.5
-65
Nominal
Maximum
4
5.5
150
Units
Volts
Volts
deg. C
Notes
1
1
1
Data Sheet #:
SG033
Page 2
of
12
Rev:
P02
Date:
11/ 22 / 04
© Copyright 2004 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Recommended Operating Specifications
Table 2
Symbol
V
CC
I
CC
T
OP
F
O
F
REF
F
CAP
F
BW
T
JTOL
T
AQ
J
GEN
Parameter
Power Supply Voltage
Power Supply Current
Temperature Range
Minimum
3.135
-
0
Nominal
3.3
-
-
-
19.44
-
8
-
100
-
Maximum
3.465
270
70
155.52
-
25
15
31.25
-
1
Units
Volts
mA
deg. C
MHz
MHz
ppm
Hz
us
ms
ps RMS
4
7
3
Notes
2, 9
5, 6
Available Output Frequencies
Q1,Q2
77.76
Reference Frequency
Capture/Pull-in Range
Jitter Filter Bandwidth
Input Jitter Tolerance
(Input Jitter Frequencies > 10 Hz)
-
-25
-
-
-
-
Acquisition Time
Jitter Generation
Q1,Q2
Input And Output Characteristics
Table 3
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
CMOS Input Characteristics
V
IH
V
IL
T
IR
T
IRF
V
OH
V
OL
C
L
T
SKEW
T
RF
DC
High Level Input Voltage
Low Level Input Voltage
Input Reference Pulse Width
Input Rise and Fall Time (20% to 80%)
High Level Output Voltage
Low Level Output Voltage
Output Capacitance
Differential Output Skew
Output Rise and Fall Time (20% to 80%)
Duty Cycle
2
0
12.5
-
2.27
1.49
-
-
-
45
-
-
-
-
2.34
1.51
-
50
-
50
5.5
0.8
-
5
2.52
1.68
10
-
1
55
V
V
nS
nS
V
V
pF
ps
ns
%
5
5
5
8
5
5
LVPECL Output Characteristics
NOTES:
1: Operation of the device at these or any other condition beyond those
listed under Recommended Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
2: Requires external regulation and supply decoupling. (22uF, 330 pF)
3: 3dB loop response.
4: From a 20 ppm step in reference frequency.
5: With LVPECL termination as defined by figure 8 (Z
O
= 50
Ω).
6: Maximum I
CC
tested at V
CC
= 3.46V
7: Jitter based on SONET OC-48 bandwidth ( 12 kHz - 20 MHz).
8: Avoid meta-stable input signals
9: Vcc ramp rate must be monotonic rising. Ramp must be greater
than 300 V/s from 2V to 3V.
Data Sheet #:
SG033
Page 3
of
12
Rev:
P02
Date:
11/ 22 / 04
© Copyright 2004 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Pin Description
Table 4
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connection
N/C
REF
TDO
GND
QN1
Q1
V
CC
GND
N/C
N/C
Q2
QN2
GND
GND
V
CC
TDI
TCK
TMS
GND
N/C
Description
Do Not Connect or Route Through
CMOS Input Reference
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Ground
Negative LVPECL Differential Output
Positive LVPECL Differential Output
Supply Voltage Relative to Ground
Ground
Do Not Connect or Route Through
Do Not Connect or Route Through
Positive LVPECL Differential Output
Negative LVPECL Differential Output
Ground
Ground
Supply Voltage Relative to Ground
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
Ground
Do Not Connect or Route Through
Package Dimensions
Figure 2
Data Sheet #:
SG033
Page 4
of
12
Rev:
P02
Date:
11/ 22 / 04
© Copyright 2004 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Recommended Footprint Dimensions
Figure 3
0.950 TYP [24.13mm]
0.050 TYP [1.27mm]
0.640 TYP [16.26mm]
0.800 TYP [20.32mm]
0.050 TYP [1.27mm]
0.080 TYP [2.03mm]
0.100 TYP [2.54mm]
Solder Profile
Figure 4
250
200
Temp
(DegC)
150
100
50
0
1
2
3
4
5
6
7
8
Time(minutes)
RecommendedReflowProfile
PeakTemp:217DegC
MaxRiseSlope:1.5Deg
C/Sec
TimeAbove150C:100Sec
Data Sheet #:
SG033
Page 5
of
12
Rev:
P02
Date:
11/ 22 / 04
© Copyright 2004 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
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