P5DF081
MIFARE SAM AV2
Rev. 1 — 12 August 2010
191710
Objective short data sheet
PUBLIC
1. General description
The NXP MIFARE SAM TM AV2 hardware solution is the ideal add-on for reader devices
offering additional security services. Supporting TDEA, AES and RSA capabilities, it offers
secure storage and secure communication in a variety of infrastructures.
Unlike other products in the field, MIFARE SAM AV2 has proven interoperability with all of
NXP's broad card portfolio, (MIFARE Ultralight, MIFARE Ultralight C, MIFARE 1K,
MIFARE 4K, MIFARE Plus, MIFARE DESFire, MIFARE DESFire EV1 and SmartMX
solutions), making it the most versatile and secure SAM solution on the market today.
Secured communication
When used in combination with a reader IC supporting innovative "X" features, MIFARE
SAM AV2 provides a significant boost in performance to the reader along with faster
communication between reader and module. The "X" feature is a new way to use the SAM
in a system, with SAM connected to the microcontroller and the reader IC simultaneously.
The connection between the SAM and the reader is performed using security protocols
based on either symmetric cryptography (TDEA and AES) or PKI RSA asymmetric
cryptography. The protocols comply with the state-of-art standards and thereby ensure
data confidentiality and integrity.
2. Features and benefits
2.1 Cryptography
Supports MIFARE Crypto1, TDEA (Triple DES encryption algorithm), RSA and AES
cryptography
Supports MIFARE Ultralight, MIFARE Ultralight C, MIFARE 1K, MIFARE 4K,
MIFARE Plus, MIFARE DESFire, MIFARE DESFire EV1
Secure storage and updating of keys (key usage counters)
128 key entries for symmetric cryptography and 3 RSA key entries for asymmetric
cryptography
TDEA and AES based key diversification
Offline cryptography
2.2 Communication
Up to four logical channels; simultaneous multiple card support
Support for DESFire and MIFARE Plus authentication (with related secure messaging
and session key generation)
NXP Semiconductors
P5DF081
MIFARE SAM AV2
Secure Host to SAM and back end to SAM communication with symmetric
cryptography 3 pass authentication for confidentiality and integrity
Support high speed baud rates up to 1.5 Mbit/s
Secure Host to SAM and back end to SAM communication with RSA based
cryptography
Support ISO/IEC 7816 baud rates
True random number generator (TRNG)
2.3 Delivery types
Available in wafer, PCM 1.1 module, or HVQFN package
3. Applications
Access management
Public transport
Loyalty programs
Micro payment
4. Quick reference data
Table 1.
Quick reference data
V
DD
; V
SS
= 0 V; T
amb
=
25
C to +85
C
Symbol
V
DD
Parameter
supply voltage
Conditions
Class A: 5 V range
Class B: 3 V range
Min
4.5
2.7
Typ
5.0
3.0
Max
5.5
3.3
Unit
V
V
5. Ordering information
Table 2.
Ordering information
Package
Name
P5DF081X0/T1AD2060
P5DF081HN/T1AD2060
PCM1.1
Description
contact chip card module (super 35 mm
tape format, 8-contact)
Version
SOT658-1
SOT617-3
Type number
HVQFN32 plastic thermal enhanced very thin quad
flat package; no leads; 32 terminals;
body 5
5
0.85 mm
P5DF081_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective short data sheet
PUBLIC
Rev. 1 — 12 August 2010
191710
2 of 36
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P5DF081_SDS
6. Block diagram
Objective short data sheet
PUBLIC
ROM
80 kB
DATA AND
PROGRAM
MEMORY
7680 B
DATA
MEMORY
ENHANCED PUBLIC
KEY
COPROCESSOR e.g.
RSA
EEPROM
RAM
264 kB
PROGRAM
MEMORY
UART
ISO 7816
MEMORY MANAGEMENT UNIT (MMU)
CLOCK
GENERATION
CPU
TIMERS
TRIPLE-DES
COPROCESSOR
CRC16
16-bit 16-bit
T0
T1
FAST
RNG
AES
COPROCESSOR
VSS
001aal646
NXP Semiconductors
IO1
IO2
PROGRAMMABLE
IO1, IO2, IO3
IO3
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 August 2010
191710
CLK
CLOCK
FILTER
RST_N
SECURITY SENSORS
RESET GENERATION
VOLTAGE REGULATOR
VDD
Fig 1. Block diagram
P5DF081
MIFARE SAM AV2
© NXP B.V. 2010. All rights reserved.
3 of 36
NXP Semiconductors
P5DF081
MIFARE SAM AV2
7. Pinning information
7.1 Pinning
V
CC
RST_N
CLK_N
n.c.
C1
C2
C3
C4
C5
C6
C7
C8
GND
IO3
IO1
IO2
001aam116
Fig 2. Pin configuration
7.2 Pin description
Table 3.
Pin description ISO/IEC 7816/MIFARE SAM AV2
MIFARE SAM AV2
Symbol
V
CC
RST_N
CLK_N
n.c.
GND
IO3
IO1
IO2
Pad
C1
C2
C3
C4
C5
C6
C7
C8
Description
power supply voltage input
reset input, active LOW
clock input
n.c.
ground (reference voltage) input
used for I2C communication to RC222 (SCLK)
input/output for serial data (host communication)
used for I2C communication to RC222 (SDATA)
ISO/IEC 7816
Pad Symbol
C1
C2
C3
C4
C5
C6
C7
C8
VCC
RST
CLK
reserved
GND
VPP
IO1
reserved
8. Functional specification
8.1 Hardware interface
8.1.1 Contact interface
The pad assignment and the electrical characteristics are fully compliant with
ISO/IEC 7816 (part 2 and part 3). The MIFARE SAM AV2 operates with Class A and
Class B interface devices. An internal charge pump provides the EEPROM programming
voltage. Note that pad C6 is not a programming voltage input but is an output line for the
clock signal for I2C communication to the RC222 reader chip. Pad C8 is used as data line
to the reader chip. These two pads for connection to the RC222 are the only ones
deviating from the ISO standard pin assignment.
8.1.2 External clock frequency and bit rates
The basic operation frequency of the MIFARE SAM AV2 is 3.5712 MHz. With this
frequency the following standard bit rates can be reached using ISO/IEC 7816
transmission factors F and D.
The MIFARE SAM AV2 supports significantly higher transmission speeds.
P5DF081_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective short data sheet
PUBLIC
Rev. 1 — 12 August 2010
191710
4 of 36
NXP Semiconductors
P5DF081
MIFARE SAM AV2
The maximum specified bit rate in any case is 1.5 Mbit/s.
8.1.3 Card operation procedures
All card operation procedures (activation, cold reset, warm reset and deactivation) are
fully compliant with
Ref. 19,
Chapter 5.
8.2 Transmission procedure and communication
8.2.1 Protocol activation sequence
All subsequently described operations are compliant with ISO/IEC 7816-3.
8.2.1.1
Answer To Reset (ATR)
The MIFARE SAM AV2 offers two modes of operation identified by different ATRs.
A negotiable mode where the bit rate has to be adjusted via a PPS request and a specific
mode where the MIFARE SAM AV2 switches automatically to F = 128 and D = 32 (highest
possible speed) after sending the ATR. Starting with the negotiable mode, the mode of
operation is switched after every warm reset.
After a cold reset, the card sends the following ATR to the terminal.
Table 4.
Character
TS
T0
TA(1)
TC(1)
TD(1)
TD(2)
TA(3)
TB(3)
TC(3)
TD(3)
TA(after T = 15)
TB(after T = 15)
Historical bytes
ATR after cold reset
Value
3Bh
DFh
18h
FFh
81h
F1h
FEh
43h
00h
3Fh
03h
83h
4Dh, 49h, 46h, 41h, 52h,
45h, 20h, 50h, 6Ch, 75h,
73h, 20h, 53h, 41h, 4Dh
3B
Meaning
initial character; setting up direct convention
TA(1), TC(1), TD(1) are present; number of
historical characters is 15
F = 372; D = 12
no extra guard time needed; N = 255
TD(2) is present; protocol T = 1
TA(3), TB(3), TC(3) and TD(3) are present; protocol
T=1
Information field size of the card = 254
BWT indicator = 4; CWT indicator = 3
error detection code = LRC
TA and TB for T = 15 is present; protocol T = 15
(qualifies global interface bytes)
clock stop not supported; Class A, Class B
Proprietary use of C6 (IO3, reception of serial data
from RC222)
ASCII value of “MIFARE Plus SAM”
TCK
check character
After this ATR, the card is in the negotiable mode and waits for a PPS request. If a warm
reset is issued, the MIFARE SAM AV2 switches the mode of operation, enters the specific
mode and sends the following ATR.
P5DF081_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective short data sheet
PUBLIC
Rev. 1 — 12 August 2010
191710
5 of 36
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