External reference Clock input or Crystal connection. This pin has dual functions. It can
be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
When SSON is HIGH, the spread spectrum is enabled and when LOW, it turns off the
spread spectrum.
No Connect.
Ground connection.
Spread Spectrum Clock Output.
No Connect.
P
O
P
Power supply for the entire chip.
Rev. 1 | Page 2 of 7 | www.onsemi.com
PCS3P2537A
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
s
T
J
T
DV
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Rating
-0.5 to +4.6
-65 to +125
260
150
2
Unit
V
°
C
°
C
°
C
KV
Voltage on any pin with respect to Ground
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
15
7
Unit
V
°
C
pF
pF
DC Electrical Characteristics for 3.3V Supply
Symbol
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Output low voltage (VDD = 3.3V, I
OL
= 8mA)
Output high voltage (VDD = 3.3V, I
OH
= 8mA)
Static supply current
Operating Voltage
Power-up time (first locked cycle after power-up)
Output impedance
1
Min
VSS-0.3
2.0
Typ
Max
0.8
VDD+0.3
-35
35
0.4
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
2.5
2.5
5
3
3.3
36
8
3.6
5
Dynamic supply current (3.3V, 27MHz and no load)
Note: 1. CLKIN is pulled to GND.
Rev. 1 | Page 3 of 7 | www.onsemi.com
PCS3P2537A
AC Electrical Characteristics for 3.3V Supply
Symbol
CLKIN
ModOUT
f
d
MR
t
LH
t
HL
1
1
Parameter
Input frequency
Output frequency
Frequency Deviation @ 27MHz
Modulation Rate @ 27MHz
Output rise time (measured from 20% to 80%)
Output fall time (measured at 80% to 20%)
Cycle-to-Cycle Jitter at 27MHz
Output duty cycle
Min
18
18
-0.2
30
Typ
27
27
-0.25
Max
36
36
-0.3
33
2
1.5
Unit
MHz
MHz
%
KHz
nS
nS
pS
%
t
JC
t
D
±200
45
50
±300
55
Note: 1. t
LH
and t
HL
are measured into a capacitive load of 15pF.
Rev. 1 | Page 4 of 7 | www.onsemi.com
PCS3P2537A
Typical Application Schematic
VDD
CLKIN / XIN
VDD
0
3
1
2
CLKIN / XIN
XOUT
VDD
8
NC
7
ModOUT
6
GND
5
0.01uF
SSON
NC
0
4
Note: Refer to Pin Description table for Functionality Details.
PCB Layout Recommendation
For optimum device performance, the following guidelines
are recommended.
•
Dedicated VDD and GND planes.
•
The device must be isolated from system power
supply noise. A 0.01µF decoupling capacitor should
be mounted on the component side of the board as
close to the VDD pin as possible. No vias should be
used between the decoupling capacitor and VDD pin.
The PCB trace to VDD pin and the ground via should
be kept as short as possible. All the VDD pins should
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