L6223A
DMOS PROGRAMMABLE
HIGH SPEED UNIPOLAR STEPPER MOTOR DRIVER
ADVANCE DATA
HIGH EFFICIENCY UNIPOLAR STEPPER
MOTOR DRIVER
HIGH SPEED UNIPOLAR STEPPER MOTOR
DRIVER
SUPPLY VOLTAGE UP TO 46V
PHASE CURRENT UP TO 1A
UP TO 2A/PHASE IN DUAL CONFIGURA-
TION
PARALLEL CMOS
µP
INTERFACE FOR
FULL/HALF STEP MOTOR ROTATION
SERIAL INTERFACE FOR 6 BIT PROGRAM-
MING
CLOSE/OPEN LOOP, 8 PWM CURRENT
LEVELS
DUAL PWM FREQUENCY SELECTION
INPUT BIDIRECTIONALLY PROTECTED
THERMAL SHUTDOWN
DESCRIPTION
The L6223A is a programmable integrated sys-
tem for driving a unipolar stepper motor. It is real-
ized in Multipower BCD technology. The DMOS
BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
POWERDIP
16+2+2
ORDERING NUMBER :
L6223A
output stage, realized by a single upper DMOS
switch and four lower DMOS, can deliver up to
1A/phase with motor supply voltages up to 46V.
All inputs are CMOS and microprocessor compat-
ible. An internal 6-bit shift register allows the de-
vice to be programmed to select different duty cy-
cles in open loop mode and different chopping
frequencies in closed loop mode. When the cur-
rent control is in closed loop mode it is also possi-
ble to select a reduced current chopping level to
optimize system efficiency. The L6223A is de-
October 1991
1/33
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6223A
signed to work with a single sense resistor. Dur-
ing chopping t(OFF) time the current is reduced
by half, improving efficiency. Higher current appli-
cations can be achieved by paralleling two
ABSOLUTE MAXIMUM RATINGS
Symbol
V
SS
V
S
V
I
V
O
V
Opeak
I
pl
I
ph
P
tot
V
sense
T
stg,
T
j
Logic supply
Supply voltage
Logic input voltage (*)
Output voltage
Output peak voltage (tpk = 5µs,10% d.c.)
Output sink peak current d.c. 10% t(on) = 10µs
Output source peak current d.c. 10%,t(on) = 10µs
Total power dissipation: T
pins
= 90°C
T
amb
= 70°C (**)
Sensing voltage
Storage and junction temperature
Parameter
Value
7
50
– 0.3V to V
SS
100
125
3
6
4.3
2
– 1V to V
SS
– 40 to 150
°C
V
V
A
A
W
W
Unit
V
V
L6223A. The L6223A is mounted in a 20-lead
Powerdip package, (16+2+2). Four ground leads
conduct heat to dedicated heatsink area on the
PCB.
( * ) Oscillator running
( ** ) 4 cm
2
copper area on PCB, see fig. 34
PIN CONNECTION
( top wiew )
THERMAL DATA
R
thj-pins
R
thj-amb
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient
Max
Max
14
60
°C/W
°C/W
2/33
L6223A
PIN DESCRIPTION
No.
1,2
18,19
3
Name
OUT2,OUT1
OUT4,OUT3
BSTP
Outputs for motor windings.
A bootstrap capacitor connected between this pin and COM will
generate the internal overvoltage required for driving the gate of the
upper DMOS.
Output for common wire of motor.
Common ground. Also provides heatsinking to PCB.
Power supply
Digital input.
1) In PROGRAM MODE,operates in XOR with DA/OPLO to load data
into 6-bit shift register.
2) In OPERATING MODE,works with the other digital inputs to reduce
the current level (see Table 2 and Table 3).
9
DA/OPLO
Digital input.
1) In PROGRAM MODE, operates in XOR with DA/CLEV to load data
into 6-bit shift register.
2) In OPERATING MODE,selects current control method: open loop (H)
or closed loop (L).
Digital inputs. When all inputs are low level,the device is in
PROGRAMMING MODE.
In OPERATING MODE:
1) FULL MODE - IN1 to IN4 drive the motor phases.
A previous programming is requested.
2) SIMPLIFIED MODE - IN1 and IN2 drive the phases,IN3 is
ENABLE, IN4 works with DA/CLEV to enable the reduce current
level. Previous programming not needed.
14
15
20
RC
V
SS
SENSE
Input for external RC network. Defines the higher of two possible
chopping frequencies. If this pin is set to ground it will reset the IC.
Logic supply.
Output for sense resistor.
Function
6
4,5
16,17
7
8
COM
GND
V
S
DA/CLEV
10,11
12,13
IN1,IN2
IN3,IN4
3/33
L6223A
ELECTRICAL CHARACTERISTICS
(T
j
= 25°C, V
S
= 42V, V
SS
= 5V, external RC network: R = 18kΩ,
C = 3.3nF, unless otherwise specified).
Symbol
V
S
V
SS
I
S
Parameter
Power Supply
Logic Supply
Power Supply Quiescent
Current
Logic Supply Quiescent
Current
Output Leakage Curr.
Reset Threshold
Voltage (Pin 14)
Bootstrap Refresh Pulse
C
BOOT
= 10nF
3
IN1, IN2, IN3, IN4 = L
RC = 0V DA/CLEV = L
DA/OPLO = L
IN1, IN2, IN3, IN4 = L
RC = 0V DA/CLEV = L
DA/OPLO = L
V
O
= 100V (Fig. 1)
Test conditions
Min
9
4.5
Typ
32
5
2
Max
46
5.5
4
Unit
V
V
mA
I
SS
14
20
mA
I
OL
V
rs
T
BOOT
1
0.9
5
mA
V
µs
SINK MOS
R
DS(ON)
ON Resistance
(Fig. 2a and Fig. 3)
1.2
Ω
SOURCE MOS
R
DS(ON)
ON Resistance
(Fig. 2b and Fig. 3)
0.7
Ω
CURRENT CONTROL SECTION
V
ref
f
(OSC)
t
(dis)
R
int
T
W
Internal Reference Volt.
Oscillator Frequency
RC Network Discharge
Time (t
ON
min)
Internal Discharge Resistor
(pin 14)
Sense Filter Time Constant
(Fig. 4)
1
DA/CLEV = L; IN4 = H
I
O
= 100% nominal value
(Fig. 20)
(Fig. 20)
0.475
18
2.3
0.5
20
3
1.2
1.4
2.3
0.525
22
4.3
V
KHz
µs
kΩ
µs
LOGIC LEVELS
V
(IN)L
V
(IN)H
Input Low Voltage
Input High Voltage
–0.3
2.4
0.8
V
SS
V
V
4/33
L6223A
ELECTRICAL CHARACTERISTICS
(Continued)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
SWITCHING TIMING
t2, t4
t1, t3
t
dPWM
Fall/Rise Time (IN1, 2, 3, 4)
Input-Output Delay
(IN1, 2, 3, 4)
Close Loop PWM
Control Delay
R
(load)
= 39
Ω
(Fig. 5)
Pure Resistive Load to V
S
R
(load)
= 39
Ω
(Fig. 5)
Pure Resistive Load to V
S
(Fig. 4) Note 1
250
700
1
ns
ns
µs
PROGRAMMING TIMING
t1
t2
t3
t4
t5
Loading Time
Protection Time
Data Set-up
Data Hold
Setting Time
(Fig. 6)
(Fig. 6) Note 2
(Fig. 6)
(Fig. 6)
(Fig. 6)
1.7
0.2
0
1.6
200
µs
µs
ns
µs
ns
Note 1) Upper DMOS turn ON delay when the signal is applied at the input comparator (point A in Fig. 4).
Note 2) Internal clock pulse is generated only if IN1...IN4 stay Low for almost 0.2
µs.
This delay avoids undesirable programmings.
Figure 1:
Output leakage I
OL
Test Circuit
Figure 2a:
Source Output DMOS R
DS(ON)
Test
Circuit
5/33
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