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AZ100LVE310FNR2

Description
Clock Driver
Categorylogic    logic   
File Size142KB,5 Pages
ManufacturerArizona Microtek
Websitehttp://azmicrotek.com
Download Datasheet Parametric View All

AZ100LVE310FNR2 Overview

Clock Driver

AZ100LVE310FNR2 Parametric

Parameter NameAttribute value
MakerArizona Microtek
package instruction,
Reach Compliance Codecompliant
ARIZONA MICROTEK, INC.
AZ100LVE310
ECL/PECL 2:8 Differential Clock Driver
FEATURES
Operating Range of 3.0V to 5.5V
Low Skew
Guaranteed Skew Spec
Differential Design
V
BB
Output
75kΩ Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC100LVE310 & MC100E310
PACKAGE AVAILABILITY
PACKAGE
PLCC 28
PLCC 28 T&R
PART NO.
AZ100LVE310FN
AZ100LVE310FNR2
MARKING
AZM100LVE310
AZM100LVE310
DESCRIPTION
The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE310 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the V
BB
reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The V
BB
pin should be used only
as a bias for the AZ100LVE310 as its current sink/source capability is limited. When used, the V
BB
pin should be
bypassed to ground via a 0.01µF capacitor.
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same V
CCO
) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
Q0
25
V
EE
CLK_SEL
26
Q0
24
Q1
23
V
CCO
22
Q1
21
Q2
20
Q2
19
18
Q3
27
17
Q3
CLKa
28
16
Q4
V
CC
CLKa
V
BB
1
Pinout: 28-Lead
PLCC (top view)
15
V
CCO
Q4
2
14
3
13
Q5
CLKb
4
5
CLKb
6
NC
7
Q7
8
V
CCO
9
Q7
10
Q6
11
Q6
12
Q5
1630 S. STAPLEY DR., SUITE 125
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
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