5962D9960601TUA datasheet, PDF

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5962D9960601TUA: DescriptionStandard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32; Categorystorage storage; File Size198KB，29 Pages; ManufacturerCobham PLC

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5962D9960601TUA Overview

Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32

5962D9960601TUA Parametric

Parameter Name	Attribute value
Maker	Cobham PLC
package instruction	DFP, FL32,.5
Reach Compliance Code	unknown
Maximum access time	100 ns
I/O type	COMMON
JESD-30 code	R-CDFP-F32
JESD-609 code	e0
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL32,.5
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Qualified
Filter level	MIL-PRF-38535 Class T
Maximum seat height	3.048 mm
Maximum standby current	0.0004 A
Minimum standby current	4.5 V
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
total dose	10k Rad(Si) V
width	12.192 mm

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REVISIONS

LTR

DESCRIPTION

Added device class Q parts and case outline X to drawing. Corrected

DATE (YR-MO-DA)

APPROVED

00-04-20

Raymond Monnin

E1 terminal symbol to

Corrected table 1 footnotes. Corrections to

paragraph 1.5 and figure 4. Added 10 second data retention table to

figure 5. - glg

Corrections to case outline X dimensions and data retention

characteristics tables. - glg

Corrections to paragraph 1.5 and addition of footnote. - glg

Corrections to sheet 16, 1 second data retention test table. - glg

Corrected CAGE code typo, 67264 changed to 67268. Updated

boilerplate. ksr

Added 02 device for -40

C to +125

C temp range. Updated

boilerplate. ksr

Boilerplate update and part of five year review. tcr

00-05-30

Raymond Monnin

00-07-26

00-08-30

02-03-18

Raymond Monnin

02-05-28

Raymond Monnin

07-12-05

Robert M. Heber

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Gary L. Gross

CHECKED BY

Jeff Bowling

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

APPROVED BY

Raymond Monnin

DRAWING APPROVAL DATE

99-09-28

REVISION LEVEL

MICROCIRCUIT, MEMORY, DIGITAL, CMOS,

512K x 8-BIT, RADIATION-HARDENED SRAM,

MONOLITHIC SILICON

SIZE

CAGE

CODE

67268

1 OF

5962-99606

5962-E097-08

SHEET

DSCC FORM 2233

APR 97

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at

http://assist.daps.dla.mil/quicksearch/

http://assist.daps.dla.mil

or from

the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q, T and V shall be in accordance with

MIL-PRF-38535, and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not effect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q, T and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 and figure 1 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.

3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4.

3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5.

3.2.6 Radiation test circuit. The radiation test circuit shall be as specified on figure 6.

3.2.7 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed.

For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and

shall be made available to the preparing or aquiring activity upon request. For device classes Q, T and V, alternate test patterns

shall be under the control of the device manufacturer’s Technology Review Board (TRB) in accordance with MIL-PRF-38535 and

shall be made available to the preparing or aquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

ambient operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q, T, and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall

be in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q, T and V shall be a "QML" or "Q" as required

in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-99606

SHEET

3.6 Certificate of compliance. For device classes Q, T and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q, T and V, the requirements of MIL-PRF-38535

and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q, T and V in MIL-PRF-38535 or

for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 41 (see MIL-PRF-38535, appendix A).

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein.

For device class T, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 and the device

manufacturer's QM plan, including screening, qualification, and conformance inspection. The performance envelope and

reliability information shall be as specified in the manufacturers QM plan.

For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

For device class T, screening shall be in accordance with the device manufacturer's QM plan, and shall be conducted on all

devices prior to qualification and technology conformance inspection.

4.2.1 Additional criteria for device class M.

Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,

and power dissipation, as applicable, in accordance with the intent specified in method 1015.

(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).

Interim and final electrical parameters shall be as specified in table IIA herein.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-99606

SHEET

5962D9960601TUA Related Products

	5962D9960601TUA	5962D9960601QUC	5962D9960601QUA	5962D9960602QUA	5962D9960601TUC	5962D9960602QUC	5962D9960602TUC
Description	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32	Standard SRAM, 512KX8, 100ns, CMOS, CDFP32, BOTTOM BRAZED, CERAMIC, DFP-32
Maker	Cobham PLC	Cobham PLC	Cobham PLC	Cobham PLC	Cobham PLC	Cobham PLC	Cobham PLC
package instruction	DFP, FL32,.5	DFP, FL32,.5	DFP, FL32,.5	DFP, FL32,.5	DFP, FL32,.5	DFP, FL32,.5	DFP, FL32,.5
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Maximum access time	100 ns	100 ns	100 ns	100 ns	100 ns	100 ns	100 ns
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-CDFP-F32	R-CDFP-F32	R-CDFP-F32	R-CDFP-F32	R-CDFP-F32	R-CDFP-F32	R-CDFP-F32
JESD-609 code	e0	e4	e0	e0	e4	e4	e4
memory density	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1
Number of terminals	32	32	32	32	32	32	32
word count	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
character code	512000	512000	512000	512000	512000	512000	512000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-40 °C	-55 °C	-40 °C	-40 °C
organize	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DFP	DFP	DFP	DFP	DFP	DFP
Encapsulate equivalent code	FL32,.5	FL32,.5	FL32,.5	FL32,.5	FL32,.5	FL32,.5	FL32,.5
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified
Filter level	MIL-PRF-38535 Class T	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class T	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class T
Maximum seat height	3.048 mm	3.048 mm	3.048 mm	3.048 mm	3.048 mm	3.048 mm	3.048 mm
Maximum standby current	0.0004 A	0.0004 A	0.0004 A	0.0004 A	0.0004 A	0.0004 A	0.0004 A
Minimum standby current	4.5 V	4.5 V	4.5 V	3 V	4.5 V	3 V	3 V
Maximum slew rate	0.1 mA	0.1 mA	0.1 mA	0.1 mA	0.1 mA	0.1 mA	0.1 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	AUTOMOTIVE	MILITARY	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	TIN LEAD	GOLD	TIN LEAD	TIN LEAD	GOLD	GOLD	GOLD
Terminal form	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
total dose	10k Rad(Si) V	10k Rad(Si) V	10k Rad(Si) V	10k Rad(Si) V	10k Rad(Si) V	10k Rad(Si) V	10k Rad(Si) V
width	12.192 mm	12.192 mm	12.192 mm	12.192 mm	12.192 mm	12.192 mm	12.192 mm
Base Number Matches	-	1	1	1	1	1	-

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