DS1010G-100 datasheet, PDF - EEWORLD Datasheet

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DS1010G-100: DescriptionSilicon Delay Line, 1-Func, 10-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14; Categorylogic logic; File Size59KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1010G-100 Overview

Silicon Delay Line, 1-Func, 10-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14

DS1010G-100 Parametric

Parameter Name	Attribute value
Maker	Maxim
Parts packaging code	DIP
package instruction	DIP,
Contacts	14
Reach Compliance Code	unknown
Other features	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT
series	1010
Input frequency maximum value (fmax)	6.25 MHz
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
length	19.05 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	10
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Total delay nominal (td)	100 ns
width	7.62 mm

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DS1010

10-Tap Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

10 taps equally spaced

Delays are stable and precise

Leading and trailing edge accuracy

Delay tolerance ±5% or ±2 ns, whichever is

greater

Economical

Auto-insertable, low profile

Standard 14-pin DIP or 16-pin SOIC

Low-power CMOS

TTL/CMOS-compatible

Vapor phase, IR and wave solderable

Custom delays available

Fast turn prototypes

IN1

TAP 2

TAP 4

TAP 6

TAP 8

GND

PIN ASSIGNMENT

TAP 1

IN1

TAP 3

TAP 5

TAP 7

TAP 9

TAP 10

TAP 2

TAP 4

TAP 6

TAP 8

GND

TAP 1

TAP 3

TAP 5

TAP 7

TAP 9

TAP 10

DS1010 14-Pin DIP (300-mil)

See Mech. Drawings Section

DS1010S 16-Pin SOIC

(300-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1 - TAP 10

GND

- TAP Output Number

- 5 Volts

- Ground

- No Connection

- Input

DESCRIPTION

The DS1010 series delay line has ten equally spaced taps providing delays from 5 ns to 500 ns. The

devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines.

Alternatively, a 16-pin SOIC is available for surface mount technology which reduces PC board area.

Since the DS1010 is an all-silicon solution, better economy is achieved when compared to older methods

using hybrid techniques. The DS1010 series delay lines provide a nominal accuracy of ±5% or ±2 ns,

whichever is greater. The DS1010 reproduces the input logic state at the TAP 10 output after a fixed

delay as specified by the dash number extension of the part number. The DS1010 is designed to produce

both leading and trailing edge with equal precision. Each tap is capable of driving up to 10 74LS type

loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests

and rapid delivery, call (972) 371-4348.

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