ASM5P23SS05A-1H-08-SR datasheet, PDF

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ASM5P23SS05A-1H-08-SR: DescriptionPLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8; Categorylogic logic; File Size664KB，15 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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ASM5P23SS05A-1H-08-SR Overview

PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8

ASM5P23SS05A-1H-08-SR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	unknown
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.92 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	5
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.8 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.95 mm
minfmax	133.33 MHz

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November 2003

rev 1.1

3.3V Peak Reducing Zero Delay Buffer

General Features

10 MHz to 133- MHz operating range, compatible

with CPU and PCI bus frequencies.

•

EMI reduced output with on-chip EMI reduction

capability.

Zero input - output propagation delay.

Multiple low-skew outputs.

•

Output-output skew less than 250 ps.

Device-device skew less than 700 ps.

One input drives 9 outputs, grouped as 4 + 4 + 1

One input drives 5 outputs (ASM5P23SS05A).

ASMP5P23SS09A

ASMP5P23SS05A

typically 1000 times slower than the fundamental clock, the

spread spectrum process has negligible impact on system

performance while giving significant cost savings. Alliance

offers options with different spreading patterns with more

spread and greater EMI reduction.

The -1H version of the ASM5P23SXXA operates at up to

133- MHz frequencies, and has higher drive than the -1

devices. All parts have on-chip PLLs that lock to an input

clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad.

The ASM5P23SS09A has two banks of four outputs each,

which can be controlled by the Select inputs as shown in

the Select Input Decoding Table. If all the output clocks are

not required, Bank B can be three-stated. The select input

also allows the input clock to be directly applied to the

outputs for chip and system testing purposes.

Multiple ASM5P23SS09A and ASM5P23SS05A devices

can accept the same input clock and distribute it. In this

case the skew between the outputs of the two devices is

guaranteed to be less than 700ps. All outputs have less

than 200 ps of cycle-to-cycle jitter. The input and output

propagation delay is guaranteed to be less than 250 ps,

and the output to output skew is guaranteed to be less than

250ps.

The ASM5P23SS09A and the ASM5P23SS05A are

available in two different configurations, as shown in the

ordering information table. The ASM5P23SXXA-1 is the

base part. The ASM5P23SXXA-1H is the high drive version

of the -1 and its rise and fall times are much faster than -1

part.

Peak Reducing

PLL

REF

CLKOUT

CLK1

CLK2

CLK3

CLK4

(ASM5P23SS09A).

Less than 200 ps cycle-to-cycle jitter is compatible with

Pentium based systems.

Test Mode to bypass PLL (ASM5P23SS09A only, refer

Select Input Decoding Table).

Available in 16-pin, 150-mil SOIC, 4.4 mm TSSOP,

and 150-mil SSOP packages (ASM5P23SS09A) or in

8-pin, 150-mil SOIC package (ASM5P23SS05A).

•

3.3V operation, advanced 0.35µ CMOS technology.

Functional Description

ASM5P23SS09A is a versatile, spread spectrum output,

3.3V zero-delay buffer designed to distribute high-speed

clocks with EMI suppression capability. It is available in a

16-pin package. The ASM5P23SS05A is the eight-pin

version of the ASM5P23SS09A. It accepts one reference

input

and

drives

out

five

low-skew

clocks.

The

ASM5P23SXXA family incorporates the latest advances in

PLL spread spectrum techniques to greatly reduce the

peak EMI by modulating the output frequency with a low

frequency carrier. The ASM5P23SXXA allows significant

system cost savings by reducing the number of circuit

board layers and shielding that are traditionally required to

pass EMI regulations. Because the modulating frequency is

Block Diagram

REF

Peak Reducing

PLL

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

S elect Inpu t

Decoding

CLKB1

CLKB2

CLKB3

CLKB4

ASM5P23SS05A

ASM5P23SS09A

Alliance Semiconductor

2575, Augustine Drive

•

Santa Clara, CA

•

Tel: 408.855.4900

•

Fax: 408.855.4999

•

www.alsc.com

Notice: The information in this document is subject to change without notice.

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