CDP68HC05P4B,
CDP68HCL05P4B,
CDP68HSC05P4B
March 1998
8-Bit Enhanced Microcontroller Series
Description
The CDP68HC05P4B HCMOS Microcomputer is a member
of the CDP68HC05 family of single chip microcomputers.
This 8-bit microcomputer unit (MCU) contains a CPU, 176
bytes of RAM, 4,160 bytes of masked ROM, a flexible 16-bit
timer with one input capture and one output compare, 20
bidirectional I/O lines and one input only line (two high cur-
rent outputs and eight mask programmable as interruptible
inputs), keypad scanning logic, a watchdog timer, a
maskable STOP instruction, and an on-chip oscillator. The
fully static design allows operation at frequencies down to
DC, further reducing the already low power consumption.
The CDP68HCL05P4B MCU device is a version of the
CDP68HC05P4B with low power consumption in the RUN,
WAIT, and STOP modes; and operation down to 2.4V. The
CDP68HSC05P4B MCU device is a high-speed version of
the CDP68HC05P4B with up to 8.0MHz operation.
The CDP68HC05P4B family supports the full CDP68HC05
instruction set. Development can be performed with tools
supplied by Intersil or offered by numerous third party ven-
dors. Available tools include assemblers and C compilers.
NOTE: Unless otherwise stated, CDP68HC05P4B refers the entire
family of P4B microcontrollers (HC, HCL, and HSC).
Features
HARDWARE
• HCMOS Technology
• 8-Bit Architecture
• Power-Saving STOP, WAIT, and Data Retention Modes
- STOP Instruction can be Disabled via Mask Option
• Fully Static Operation
• On-Chip Memory
- 4,160 Bytes of ROM
- 176 Bytes of RAM
• ROM Security Feature
• 20 Bidirectional I/O Lines, 1 Input-Only Line
- 2 High Current Outputs (PC0 and PC1)
- 8 Interruptible Inputs (with Pull-Up Resistors) - Port A
- Schmitt Trigger Inputs on Port A
• Watchdog Timer (COP)
• Low Power Wake Up Timer
• Internal 16-Bit Timer
- 1 Timer Capture
- 1 Timer Compare
• Interrupts - External, Port A, Software, and Timer
• Master Reset and Power-On Reset
• On-Chip Oscillator with RC or Crystal Mask Options
• CDP68HC05P4B
- 4.2MHz Operating Frequency (2.1MHz Internal Bus
Frequency) at 5V; 2MHz at 3.0V
- Single 3.0V to 6.0V Supply (1.2V Data Retention)
• CDP68HCL05P4B
- Lower Supply Current, I
DD
, In RUN, WAIT and STOP
Modes at 5.5V, 3.3V and 2.4V
- Single 2.4V to 6.0V Supply (1.2V Data Retention)
• CDP68HSC05P4B
- 8.0MHz Operating Frequency (4.0MHz Internal Bus
Frequency) at 5.0V; 4.2MHz at 3.3V
- Single 3.0V to 6.0V Supply (1.2V Data Retention)
SOFTWARE
• Supports Full CDP68HC05 Instruction Set
• 8 x 8 Unsigned Multiply Instruction
• True Bit-Manipulation
• Two Power Saving Standby Modes
• Memory Mapped I/O
Table of Contents
Ordering Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinouts.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical & Timing Specifications
. . . . . . . . . . . . . . . . . 4
Typical Performance Curves
. . . . . . . . . . . . . . . . . . . . . 17
Functional Pin Description
. . . . . . . . . . . . . . . . . . . . . . 18
Input/Output Programming
. . . . . . . . . . . . . . . . . . . . . . 19
Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Resets, Interrupts and Low Power Modes
. . . . . . . . . . 23
Hardware/Power-On Resets . . . . . . . . . . . . . . . . . . . . . 23
COP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Wake Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Self Check Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programmable Timer
. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Compare Register . . . . . . . . . . . . . . . . . . . . . . . 32
Input Capture Register. . . . . . . . . . . . . . . . . . . . . . . . . . 32
Simple Serial Input/Output Port (SIOP).
. . . . . . . . . . . . 34
Effects of STOP and WAIT modes.
. . . . . . . . . . . . . . . . 36
Package Outline Dimensions.
. . . . . . . . . . . . . . . . . . . . 37
CDP68HC05 Family Feature Comparison.
. . . . . . . . . . 40
Opcode Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I/O, Control, Status and Data Register Definitions
. . . 42
Ordering Information Sheet
. . . . . . . . . . . . . . . . . . . . . . 43
File Number
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
©
Intersil Corporation 1999
4345.1
1
CDP68HC05P4B, CDP68HCL05P4B, CDP68HSC05P4B
Ordering Information
PART NUMBER
CDP68HC05P4BM20
CDP68HC05P4BE28
CDP68HC05P4BM28
CDP68HCL05P4BM20
CDP68HCL05P4BE28
CDP68HCL05P4BM28
CDP68HSC05P4BM20
CDP68HSC05P4BE28
CDP68HSC05P4BM28
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
PACKAGE
20 Ld SOIC
28 Ld PDIP
28 Ld SOIC
20 Ld SOIC
28 Ld PDIP
28 Ld SOIC
20 Ld SOIC
28 Ld PDIP
28 Ld SOIC
PKG.
NO.
M20.3
E28.6
M28.3
M20.3
E28.6
M28.3
M20.3
E28.6
M28.3
Regardless of the medium used to transfer the data, con-
tents of all of the User ROM regions of the memory map of
the particular microcontroller should be specified. This
includes any Page 0 User ROM and User Reset/Interrupt
Vectors. Data should not be specified for the Self Check
ROM space of a device. All unused locations should either
not be specified (S-Record and source files) or specified as
$00 (EPROM/EEPROM).
Procedure for Submitting Data
When submitting data via a physical medium such as a
floppy disk or EPROM, the appropriate “Ordering Informa-
tion Sheet” on the back pages must be completed and sub-
mitted with the data.
If the data is submitted via email, the message should
include the same information as that specified on the “Order-
ing Information Sheet”.
NOTE: Pin number references throughout this specification refer to
the 28 lead DIP/SOIC. See pinouts for cross reference.
ROM Ordering Information
The CDP68HC05P4B family of microcontrollers contains a
mask programmed ROM. The contents of this ROM is per-
sonalized to meet a customer’s code requirements during
manufacturing of the ICs. The code is programmed via pho-
tomasking techniques. Semiconductor manufacturing is a
batch process, and all microcontrollers manufactured in a
given lot (a batch) will contain identical ROM code.
Intersil generates a customer’s ROM mask from an ASCII
representation of the desired ROM contents together with
other specific information. The back page contains sheets
which can be used to provide the required information when
ordering a masked ROM microcontroller.
Data Format Options
The ROM data can be submitted in various formats. The fol-
lowing list summarizes the principal formats which Intersil
will accept. The list is in order of preference, with S-Record
formatted data files being the preferred format.
• S-Record Formatted Hex Data File via Modem Upload
• S-Record Formatted Hex Data File on Floppy Disk
• S-Record Formatted Hex Data File via email
• 6805 Assembly Language Source File on Floppy Disk
• Contents of a 27XX type EPROM/EEPROM
2
CDP68HC05P4B, CDP68HCL05P4B, CDP68HSC05P4B
Pinouts
CDP68HC05P4B, CDP68HCL05P4B, CDP68HSC05P4B
(SOIC, PDIP)
TOP VIEW
RESET 1
IRQ 2
PA7 3
PA6 4
PA5 5
PA4 6
PA3 7
PA2 8
PA1 9
PA0 10
SDO/PB5 11
SDI/PB6 12
SCK/PB7 13
V
SS
14
28 V
DD
27 OSC1
26 OSC2
25 TCAP/PD7
24 TCMP
23 PD5
22 PC0
21 PC1
20 PC2
19 PC3
18 PC4
17 PC5
16 PC6
15 PC7
CDP68HC05P4B, CDP68HCL05P4B, CDP68HSC05P4B
(SOIC ONLY)
TOP VIEW
IRQ
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
1
2
3
4
5
6
7
8
9
20 RESET
19 V
DD
18 OSC1
17 OSC2
16 PC0
15 PC1
14 PC2
13 PC3
12 PC4
11 PC5
V
SS
10
NOTE: Low EMI pinouts are available for these devices. Please refer to Intersil Tech Brief TB354 for more information.
Block Diagram
PD5
PD7/TCAP
PORT
D
REG
DATA
DIR
REG
OSC1
INTERNAL
PROCESSOR
CLOCK
OSC2
TCMP
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
TIMER SYSTEM
OSCILLATOR
AND
÷
2
COP SYSTEM
WAKE UP TIMER
ACCUMULATOR
PORT
C
REG
DATA
DIR
REG
8
8
5
6
5
8
INDEX
REGISTER
CONDITION CODE
REGISTER
STACK
POINTER
A
X
CC
SP
CPU
CONTROL
RESET
IRQ
CPU
DATA
DIR
REG
ALU
PORT
B
REG
SDO/PB5
SDI/PB6
SCK/PB7
SIOP
PORT
A
REG
DATA
DIR
REG
PROGRAM
COUNTER HIGH PCH
PROGRAM
COUNTER LOW
PCL
4160 x 8
ROM
176 x 8
STATIC RAM
3
CDP68HC05P4B Electrical Specifications
Absolute Maximum Ratings
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . V
SS
- 0.3V to V
DD
+ 0.3V
Self-Check Mode (IRQ Pin Only), V
IN
. . .V
SS
- 0.3V to 2 x V
DD
+ 0.3V
Current Drain Per Pin Excluding V
DD
and V
SS
, I . . . . . . . . . . . 40mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
28 Ld PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
o
20 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
o
28 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range (T
STG
) . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.0V
Temperature Range
CDP68HC05P4B . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CDP68HCL05P4B . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
CDP68HSC05P4B . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . (0.8 x V
DD
) to V
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
CDP68HC05P4B
Output Voltage
HC Product Type , V
DD
= 5.0V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= -40
o
C to 85
o
C (Note 2)
V
OL
V
OH
I
LOAD
< 10µA
-
V
DD
- 0.1
-
-
0.1
-
V
V
Output High Voltage
PA0-7. PB5-7, PC2-7, PD5
PC0-1
Output Low Voltage
PA0-7. PB5-7, PC2-7, PD5
PC0-1
Input High Voltage
PA0-7, PB5-7, PC0-7, PD5, PD7/TCAP,
RESET, IRQ, OSC1
Input Low Voltage
PA0-7, PB5-7, PC0-7, PD5, PD7/TCAP,
RESET, IRQ, OSC1
Data Retention Mode
Supply Current
RUN (Note 6)
WAIT (Notes 7, 9)
STOP (Note 8)
STOP (Note 8)
STOP with Wake Up Timer Enabled
Wake Up Timer RC Oscillator Frequency
I/O Ports Hi-Z Leakage Current:
PA0-7. PB5-7, PC0-7, PD5
Input Current: RESET, IRQ, OSC1, TCAP/PD7
Capacitance Ports (As Input or Output, Note 3)
RESET, IRQ, OSC1
I
IL
I
IN
C
OUT
C
IN
-
-
-
-
-
-
-
-
±10
±1
12
8
µA
µA
pF
pF
I
DD
I
DD
I
DD
I
DD
I
DD
f
RCO
f
OSC
= 4.2MHz
External Square Wave
T
A
= 25
o
C
T
A
= -40
o
C to 85
o
C
T
A
= 25
o
C
T
A
= 25
o
C
-
-
-
-
-
-
3.1
1.1
1.0
4.0
10
13
5
3.5
15
30
-
-
mA
mA
µA
µA
µA
kHz
V
IL
V
RM
T
A
= 0
o
C to 70
o
C
V
SS
1.2
-
-
0.2•V
DD
-
V
V
V
IH
0.7•V
DD
-
V
DD
V
V
OL
V
OL
I
LOAD
= 1.6mA
I
LOAD
= 15.0mA
-
-
-
-
0.4
0.4
V
V
V
OH
V
OH
I
LOAD
= -0.8mA
I
LOAD
= -5.0mA
V
DD
- 0.8
V
DD
- 0.8
-
-
-
-
V
V
4
CDP68HC05P4B Electrical Specifications
DC Electrical Specifications
PARAMETER
Input Pullup Current (Note 10)
Input Hysteresis Voltage: PA0-7
Input Hysteresis Voltage: RESET, IRQ, OSC1,
TCAP
HC Product Type , V
DD
= 5.0V
(Continued)
SYMBOL
I
IN
V
HYS
V
HYS
CONDITIONS
MIN
5
-
0.1•V
DD
0.5
1.0
TYP
MAX
250
-
0.5•V
DD
UNITS
µA
V
V
Control Timing HC Product Type, V
DD
= 5.0V
PARAMETER
CDP68HC05P4B
V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= -40
o
C to 85
o
C
Frequency Of Operation
Crystal Option
External Clock Option
Internal Operating Frequency
Crystal (f
OSC
÷
2)
External Clock (f
OSC
÷
2)
Cycle Time (See Figure 15)
Crystal Oscillator Start-up Time for AT-cut Crystal (See Figure 15)
Stop Recovery Start-up Time (AT-cut Crystal Oscillator) (See Figure 1)
f
OP
f
OP
t
CYC
t
OXOV
t
ILCH
t
RL
-
DC
476
-
-
1.5
2.1
2.1
-
100
100
-
MHz
MHz
ns
ms
ms
t
CYC
f
OSC
f
OSC
-
DC
4.2
4.2
MHz
MHz
SYMBOL
MIN
MAX
UNITS
RESET
Pulse Width (See Figure 15)
Timer
Resolution (Note 12)
Input Capture Pulse Width (See Figures 2, 23)
Input Capture Pulse Period (See Figures 2, 23)
Interrupt Pulse Width Low (Edge-Triggered) (See Figure 16B)
Interrupt Pulse Period (See Figure 16B)
OSC1 Pulse Width
t
RES
t
TH
, t
TL
t
TLTL
t
ILIH
t
ILIH
t
OH
, t
OL
4
125
(Note 13)
125
(Note11)
90
-
-
-
-
-
-
t
CYC
ns
t
CYC
ns
t
CYC
ns
DC Electrical Specifications
PARAMETER
HC Product Type , V
DD
= 3.3V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CDP68HC05P4B
V
DD
= 3.3V
±10%,
V
SS
= 0V, T
A
= -40
o
C to 85
o
C (Note 2)
Output Voltage
V
OL
V
OH
Output High Voltage
PA0-7. PB5-7, PC2-7, PD5
PC0-1
Output Low Voltage
PA0-7. PB5-7, PC2-7, PD5
PC0-1
Input High Voltage
PA0-7, PB5-7, PC0-7, PD5, PD7/TCAP,
RESET, IRQ, OSC1
V
IH
0.7•V
DD
-
V
DD
V
V
OL
V
OL
I
LOAD
= 0.4mA
I
LOAD
= 6.0mA
-
-
-
-
0.3
0.3
V
V
V
OH
V
OH
I
LOAD
= -0.2mA
I
LOAD
= -1.5mA
V
DD
- 0.3
V
DD
- 0.3
-
-
-
-
V
V
I
LOAD
< 10µA
-
V
DD
- 0.1
-
-
0.1
-
V
V
5
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