AD73322LARU-REEL datasheet, PDF

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> AD73322LARU-REEL

AD73322LARU-REEL: DescriptionSPECIALTY TELECOM CIRCUIT, PDSO28, MO-153AE, TSSOP-28; CategoryWireless rf/communication Telecom circuit; File Size3MB，49 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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AD73322LARU-REEL Overview

SPECIALTY TELECOM CIRCUIT, PDSO28, MO-153AE, TSSOP-28

AD73322LARU-REEL Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	28
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	9.7 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
Certification status	COMMERCIAL
Maximum seat height	1.2 mm
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm

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AD73322L

TABLE OF CONTENTS

Specifications..................................................................................... 4

Current Summary......................................................................... 6

Signal Ranges ................................................................................ 7

Timing Characteristics ................................................................ 7

Timing Diagrams.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Terminology .................................................................................... 12

Abbreviations .............................................................................. 12

Typical Performance Characteristics and Functional Block

Diagram ........................................................................................... 13

Functional Descriptions ................................................................ 14

Encoder Channels ...................................................................... 14

Programmable Gain Amplifier................................................. 14

ADC ............................................................................................. 14

Analog Sigma-Delta Modulator ............................................... 14

Decimation Filter........................................................................ 15

ADC Coding ............................................................................... 15

Decoder Channel........................................................................ 16

DAC Coding................................................................................ 16

Interpolation Filter ..................................................................... 16

Analog Smoothing Filter and PGA.......................................... 16

Differential Output Amplifiers................................................. 16

Voltage Reference ....................................................................... 16

Analog and Digital Gain Taps................................................... 17

Digital Gain Tap.......................................................................... 18

Serial Port (SPORT) ................................................................... 18

SPORT Overview........................................................................ 18

SPORT Register Maps................................................................ 19

Master Clock Divider................................................................. 19

Serial Clock Rate Divider .......................................................... 19

Rev. A | Page 2 of 48

Sample Rate Divider................................................................... 19

DAC Advance Register .............................................................. 20

Control Register A ..................................................................... 21

Control Register B...................................................................... 21

Control Register C...................................................................... 21

Control Register D ..................................................................... 22

Control Register E ...................................................................... 22

Control Register F ...................................................................... 22

Control Register G ..................................................................... 23

Control Register H ..................................................................... 23

Operation......................................................................................... 24

Resetting the AD73322L ........................................................... 24

Power Management ................................................................... 24

Operating Modes........................................................................ 24

Program (Control) Mode .......................................................... 24

Data Mode................................................................................... 25

Mixed Program/Data Mode...................................................... 25

Digital Loop-Back Mode........................................................... 25

SPORT Loop-Back Mode.......................................................... 25

Analog Loop-Back Mode .......................................................... 26

Interfacing ....................................................................................... 27

Cascade Operation..................................................................... 27

Performance .................................................................................... 29

Encoder Section.......................................................................... 29

Encoder Group Delay ................................................................ 30

Decoder Section ......................................................................... 30

On-Chip Filtering....................................................................... 31

Decoder Group Delay................................................................ 31

Design Considerations................................................................... 32

Analog Inputs ............................................................................. 32

Interfacing to an Electret Microphone .................................... 34

AD73322L

Analog Output.............................................................................34

Differential-to-Single-Ended Output .......................................35

Digital Interfacing .......................................................................35

Cascade Operation......................................................................35

Grounding and Layout ...............................................................36

DSP Programming Considerations ..............................................37

DSP SPORT Configuration .......................................................37

DSP SPORT Interrupts...............................................................37

DSP Software Considerations When Interfacing to the

AD73322L ....................................................................................37

Operating Mode ..........................................................................37

Mixed-Mode Operation.............................................................37

Interrupts .....................................................................................37

Initialization.................................................................................38

Running the AD73322L with ADCs or DACs in Power-Down

.......................................................................................................38

DAC Timing Control Example .....................................................40

Configuring an AD73322L to Operate in Data Mode ...............41

Configuring an AD73322L to Operate in Mixed Mode ............43

Outline Dimensions........................................................................46

Ordering Guide ...........................................................................47

REVISION HISTORY

12/04—Rev. 0 to Rev. A

Updated Format.................................................................. Universal

Updated Outline Dimensions........................................................46

Changes to Ordering Guide...........................................................47

4/01—Revision 0: Initial Version

Rev. A | Page 3 of 48

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