MBM29DL800TA-12PBT-SF2 datasheet, PDF

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MBM29DL800TA-12PBT-SF2: DescriptionFlash, 512KX16, 120ns, PBGA48,; Categorystorage storage; File Size601KB，59 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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MBM29DL800TA-12PBT-SF2 Overview

Flash, 512KX16, 120ns, PBGA48,

MBM29DL800TA-12PBT-SF2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SPANSION
package instruction	FBGA, BGA48,6X8,32
Reach Compliance Code	unknown
Maximum access time	120 ns
Spare memory width	8
startup block	TOP
command user interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B48
JESD-609 code	e0
memory density	8388608 bit
Memory IC Type	FLASH
memory width	16
Number of departments/size	2,4,2,14
Number of terminals	48
word count	524288 words
character code	512000
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA48,6X8,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Certification status	Not Qualified
ready/busy	YES
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.045 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20860-3E

FLASH MEMORY

CMOS

8M (1M

8/512K

16) BIT

MBM29DL800TA

-70/-90/-12

/MBM29DL800BA

-70/-90/-12

FEATURES

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Simultaneous operations

Read-while-Erase or Read-while-Program

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV800TA/BA)

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

48-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

Two 16K byte, four 8K bytes, two 32K byte, and fourteen 64K bytes.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V

write inhibit

≤

2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

(Continued)

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29DL800TA

-70/-90/-12

/MBM29DL800BA

-70/-90/-12

GENERAL DESCRIPTION

The MBM29DL800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K

words of 16 bits each. The MBM29DL800TA/BA are offered in a 48-pin TSOP(I) and 48-ball FBGA packages.

These devices are designed to be programmed in-system with the standard system 3.0 V V

supply. 12.0 V

and 5.0 V V

are not required for write or erase operations. The devices can also be reprogrammed in

standard EPROM programmers.

MBM29DL800TA/BA provides simultaneous operation which can read a data while program/erase. The

simultaneous operation architecture provides simultaneous operation by dividing the memory space into two

banks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously

read from the other bank.

The standard MBM29DL800TA/BA offer access times 70 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29DL800TA/BA are pin and command set compatible with JEDEC standard E

PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29DL800TA/BA are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29DL800TA/BA are erased when shipped from the

factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29DL800TA/BA memories electrically erase the entire chip

or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29DL800TA-12PBT-SF2 Related Products

	MBM29DL800TA-12PBT-SF2	MBM29DL800BA-12PBT-SF2	MBM29DL800BA-12PFTR
Description	Flash, 512KX16, 120ns, PBGA48,	Flash, 512KX16, 120ns, PBGA48,	Flash, 512KX16, 120ns, PDSO48,
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	SPANSION	SPANSION	SPANSION
Reach Compliance Code	unknown	unknown	not_compliant
Maximum access time	120 ns	120 ns	120 ns
Spare memory width	8	8	8
startup block	TOP	BOTTOM	BOTTOM
command user interface	YES	YES	YES
Data polling	YES	YES	YES
JESD-30 code	R-PBGA-B48	R-PBGA-B48	R-PDSO-G48
JESD-609 code	e0	e0	e0
memory density	8388608 bit	8388608 bit	8388608 bit
Memory IC Type	FLASH	FLASH	FLASH
memory width	16	16	16
Number of departments/size	2,4,2,14	2,4,2,14	2,4,2,14
Number of terminals	48	48	48
word count	524288 words	524288 words	524288 words
character code	512000	512000	512000
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
organize	512KX16	512KX16	512KX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	FBGA	TSSOP
Encapsulate equivalent code	BGA48,6X8,32	BGA48,6X8,32	TSSOP48,.8,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
power supply	3/3.3 V	3/3.3 V	3/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
ready/busy	YES	YES	YES
Department size	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K
Maximum standby current	0.000005 A	0.000005 A	0.000005 A
Maximum slew rate	0.045 mA	0.045 mA	0.045 mA
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM	DUAL
switch bit	YES	YES	YES
type	NOR TYPE	NOR TYPE	NOR TYPE
package instruction	FBGA, BGA48,6X8,32	FBGA, BGA48,6X8,32	-

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