531FA414M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531FA414M000DG

531FA414M000DG: DescriptionLVDS Output Clock Oscillator, 414MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531FA414M000DG Overview

LVDS Output Clock Oscillator, 414MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531FA414M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	414 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Two-channel power amplifier integrated circuit

Output 85 to 145V adjustable regulated power supply circuit

Contactless reversible shifting regulated power supply

88 to 108MHz FM signal generator circuit

Charging circuit with reverse connection display

A comprehensive protection circuit using the principle of UCE increase when IGBT is short-circuited and current sensor detection

How to build a wince5.0 development environment with win7 x64 + VS2008: After I installed wince 5.0 sdk, I found the sdk in vs, but there is no simulator. I can't install the simulator even if I download it. It always prompts an error. The most important pb is also missin...; YUZHIZUI Embedded System

ATmega16 prescaler usage problem: In the chip manual, it is described that TC0 and TC1 share a prescaler, but can have different frequency division settings. I would like to ask the seniors who are familiar with 16, how do you underst...; 不见曦月 MCU

Special Discussion on Resonant Converters: The prototype of the resonant converter appeared in the early 20th century. Many power electronic devices based on mercury arc rectifiers and later SCR devices work in a resonant mode in order to obta...; zbz0529 Power technology

Comparison of TCP and UDP in GPRS/CDMA Industry Applications: The GPRS network and CDMA network promoted by China Mobile and China Unicom have covered a large number of areas, making it possible to realize data transmission through wireless networks. Wireless Mo...; totopper Industrial Control Electronics

Can ifeq and ifneq be nested in makefile?: ifneq（A,B） ifneq（C,D） ifneq（E,F） a statement b statement c statement endif endif endif If A=B, will it jump out directly? If A=B is false (ifneq（A,B） is true), C=D is true, which statement is executed...; 与非门 Embedded System

DIY High Power Radio Transmitter: [[i] This post was last edited by Qingye Piaoling on 2012-4-1 22:16[/i]]...; 青叶漂零 DIY/Open Source Hardware

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components