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MC10EP56, MC100EP56
3.3V / 5V ECL Dual
Differential 2:1 Multiplexer
Description
The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple V
BB
pins are
provided.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The device features both individual and common select inputs to
address both data path and random logic applications.
The 100 Series contains temperature compensation.
Features
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MARKING DIAGRAMS*
20
MC100EP56
AWLYYWWG
SOIC−20
DW SUFFIX
CASE 751D
1
•
360 ps Typical Propagation Delays
•
Maximum Frequency > 3 GHz Typical
•
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
•
•
•
•
•
•
•
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−5.5
V
Open Input Default State
Safety Clamp on Inputs
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Outputs
Pb−Free Packages are Available
TSSOP−20
DT SUFFIX
CASE 948R
XXXX
EP56
ALYWG
G
20
1
XXXX
EP56
ALYWG
G
QFN−20
MN SUFFIX
CASE 485E
xxxx
D
A
L, WL
Y, YY
W, WW
G,
G
= MC10 or 100
= Date Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
November, 2008
−
Rev. 15
1
Publication Order Number:
MC10EP56/D
MC10EP56, MC100EP56
COM_SEL
Table 1. PIN DESCRIPTION
PIN
SEL1
15
V
CC
14
Q1
13
Q1
12
V
EE
11
D0a*
−
D1a*
D0a*
−
D1a*
D0b*
−
D1b*
D0b*
−
D1b*
SEL0*
−
SEL1*
COM_SEL*
V
BB0
, V
BB1
Q0
−
Q1
Q0
−
Q1
V
CC
V
EE
EP
FUNCTION
ECL Input Data a
ECL Input Data a Invert
ECL Input Data b
ECL Input Data b Invert
ECL Indiv. Select Input
ECL Common Select Input
Output Reference Voltage
ECL True Outputs
ECL Inverted Outputs
Positive Supply
Negative Supply
Exposed Pad
V
CC
20
Q0
19
Q0
18
SEL0
17
16
1
0
1
0
1
D0a
2
D0a
4
V
BBO
D0b
3
5
D0b
6
7
D1a D1a
8
V
BB1
9
D1b
10
D1b
* Pins will default LOW when left open.
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Table 2. TRUTH TABLE
SEL0
X
L
L
H
H
SEL1
X
L
H
H
L
COM_SEL
H
L
L
L
L
Q0,
Q0
a
b
b
a
a
Q1,
Q1
a
b
a
a
b
Figure 1. 20−Lead Package
(Top View)
and Logic Diagram
Exposed Pad
D0a
20
D0a V
CC
19
18
Q0
17
Q0
16
V
BB0
D0b
D0b
D1a
D1a
1
2
3
4
5
MC10/100EP56
15
14
13
12
11
SEL0
COM_SEL
SEL1
V
CC
Q1
6
NOTE:
7
8
9
10
V
BB1
D1b D1b V
EE
Q1
The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to V
EE
.
Figure 1. QFN−20 Pinout
(Top View)
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2
MC10EP56, MC100EP56
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 1
Level 1
N/A
Value
75 kW
N/A
> 2 kV
> 150 V
> 2 kV
Pb−Free Pkg
Level 3
Level 3
Level 1
Value
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC
TSSOP
QFN
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
140 Devices
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
20 TSSOP
20 TSSOP
20 TSSOP
20 SOIC
20 SOIC
20 SOIC
QFN−20
QFN−20
QFN−20
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
6
−6
6
−6
50
100
±
0.5
−40
to +85
−65
to +150
140
100
23 to 41
90
60
33 to 35
47
33
18
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10EP56, MC100EP56
Table 5. 10EP DC CHARACTERISTICS, PECL
V
CC
= 3.3 V, V
EE
= 0 V (Note 2)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
Input HIGH Current
Input LOW Current
−150
Min
50
2165
1365
2090
1365
1790
2.0
1890
Typ
61
2290
1490
Max
75
2415
1615
2415
1690
1990
3.3
Min
50
2230
1430
2155
1460
1855
2.0
1955
25°C
Typ
63
2355
1555
Max
75
2480
1680
2480
1755
2055
3.3
Min
55
2290
1490
2215
1490
1915
2.0
2015
85°C
Typ
65
2415
1615
Max
78
2540
1740
2540
1815
2115
3.3
Unit
mA
mV
mV
mV
mV
mV
V
I
IH
I
IL
150
−150
150
−150
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to
−2.2
V.
3. All loading with 50
W
to V
CC
−
2.0 V.
4. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL
V
CC
= 5.0 V, V
EE
= 0 V (Note 5)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
Input HIGH Current
Input LOW Current
−150
Min
50
3865
3065
3790
3065
3490
2.0
3590
Typ
61
3990
3190
Max
75
4115
3315
4115
3390
3690
5.0
Min
50
3930
3130
3855
3130
3555
2.0
3655
25°C
Typ
63
4055
3255
Max
75
4180
3380
4180
3455
3755
5.0
Min
55
3990
3190
3915
3190
3615
2.0
3715
85°C
Typ
65
4115
3315
Max
78
4240
3440
4240
3515
3815
5.0
Unit
mA
mV
mV
mV
mV
mV
V
I
IH
I
IL
150
−150
150
−150
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +2.0 V to
−0.5
V.
6. All loading with 50
W
to V
CC
−
2.0 V.
7. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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