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S29JL032H70TAI3230

Description
Flash
Categorystorage    storage   
File Size2MB,58 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

S29JL032H70TAI3230 Overview

Flash

S29JL032H70TAI3230 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Reach Compliance Codecompliant
Memory IC TypeFLASH
Programming voltage3 V
S29JL032H
32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V
Simultaneous Read/Write Flash
Distinctive Characteristics
Simultaneous Read/Write Operations
– Data can be continuously read from one bank while executing
erase/program functions in another bank.
– Zero latency between read and write operations
Multiple Bank Architecture
– Four bank architectures available (refer to
Table on page 11).
Boot Sectors
– Top and bottom boot sectors in the same device
– Any combination of sectors can be erased
Manufactured on 0.13 µm Process Technology
Secured Silicon Sector:
Extra 256 Byte sector
Customer lockable:
One-time programmable only. Once locked,
data cannot be changed
Zero Power Operation
– Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
Compatible with JEDEC standards
– Pinout and software compatible with single-power-supply flash
standard
Package options
48-pin TSOP
Performance Characteristics
High Performance
– Access time as fast as 60 ns
– Program time: 4 µs/word typical using accelerated programming
function
Ultra Low Power Consumption (typical values)
– 2 mA active read current at 1 MHz
– 10 mA active read current at 5 MHz
General Description
The S29JL032H is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to
be programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard EPROM programmers.
The device is available with an access time of 60, 70, or 90 ns and is offered in a 48-pin TSOP package. Standard control pins—
chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus
contention issues.
The device requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
Cypress Semiconductor Corporation
Document Number: 002-01186 Rev. *A
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Cycling Endurance: 1 million cycles per sector typical
Data Retention: 20 years typical
Architectural Advantages
– 200 nA in standby or automatic sleep mode
Software Features
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
– Suspends erase operations to read data from, or program data to,
a sector that is not being erased, then resumes the erase
operation.
Data# Polling and Toggle Bits
– Provides a software method of detecting the status of program or
erase cycles
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple
program command sequences
Hardware Features
Ready/Busy# Output (RY/BY#)
– Hardware method for detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method of resetting the internal state machine to the
read mode
WP#/ACC Input Pin
– Write protect (WP#) function protects the two outermost boot
sectors regardless of sector protect status
– Acceleration (ACC) function accelerates program timing
Sector Protection
– Hardware method to prevent any program or erase operation
within a sector
– Temporary Sector Unprotect allows changing data in protected
sectors in-system
Th
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San Jose
,
CA 95134-1709
408-943-2600
Revised December 08, 2015
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