IS41C16257
IS41LV16257
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
•
•
•
•
•
•
Fast access and cycle time
TTL compatible inputs and outputs
Refresh Interval: 512 cycles/8 ms
Refresh Mode:
RAS
-Only,
CAS
-before-
RAS
(CBR),
and Hidden
JEDEC standard pinout
Single power supply:
-- 5V
±
10% (IS41C16257)
-- 3.3V
±
10% (IS41LV16257)
Byte Write and Byte Read operation via two
CAS
Industrial temperature available
ISSI
MAY 1999
®
DESCRIPTION
The
ISSI
IS41C16257 and the IS41LV16257 are 262,144
x 16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 512 random accesses
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
byte, makes these devices ideal for use in 16- and 32-bit
wide data bus systems.
These features make the IS41C16257 and the IS41LV16257
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C16257 and the IS41LV16257 are packaged in a
40-pin, 400-mil SOJ and TSOP (Type II).
•
•
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
1
IS41C16257
IS41LV16257
FUNCTIONAL DESCRIPTION
The IS41C16257 and the IS41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (
RAS
). The column address is
latched by the Column Address Strobe (
CAS
).
RAS
is used
to latch the first nine bits and
CAS
is used to latch the latter
nine bits.
The IS41C16257 and the IS41LV16257 has two
CAS
controls,
LCAS
and
UCAS
. The
LCAS
and
UCAS
inputs
internally generate a
CAS
signal functioning in an identical
manner to the single
CAS
input on the other 256K x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls
I/O0 - I/O7 and
UCAS
controls I/O8 - I/O15.
The IS41C16257 and the IS41LV16257
CAS
function is
determined by the first
CAS
(
LCAS
or
UCAS
) transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16257 both BYTE READ and BYTE
WRITE cycle capabilities.
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle
must not be initiated until the minimum precharge time t
RP
,
t
CP
has elapsed.
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is dependent
ISSI
on the timing relationships between these parameters.
®
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the ad-
dressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
, while
holding
CAS
LOW. In
CAS
-before-
RAS
refresh cycle, an
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Memory Cycle
Power-On
After application of the V
CC
supply, an initial pause of
200
µs
is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
IS41C16257
IS41LV16257
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
–0.5 t0 +4.6
–1.0 to +7.0
–0.5 t0 +4.6
50
1
0 to 70
–40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
ISSI
®
Com.
Ind.
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND)
Symbol
V
CC
V
CC
V
IH
V
IH
V
IL
V
IL
T
A
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Ambient Temperature
Voltage
5V
3.3V
5V
3.3V
5V
3.3
Com.
Ind.
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
0
–40
Typ.
5.0
3.3
—
—
—
—
—
—
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
V
V
V
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A8
Input Capacitance:
RAS
,
UCAS
,
LCAS
,
WE
,
OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
CC
= 5.0V + 10% or Vcc=3.3V
±
10%.
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
5
京公网安备 11010802033920号
EEWORLD
