SSTUM32868
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for
DDR2-800 RDIMM applications
Rev. 02 — 2 March 2007
Product data sheet
1. General description
The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
by four (2R
×
4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUM32868 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently
configured for high output drive strength. This allows use in high density designs with
heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two
additional chip select inputs, which allow more versatile enabling and disabling in densely
populated memory modules. Both added features (drive strength and chip selects) are
fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is
optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUM32868 is packaged in a 176-ball, 8
×
22 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
6 mm
×
15 mm of board space) allows for adequate signal routing and escape using
conventional card technology.
2. Features
I
28-bit data register supporting DDR2
I
Fully compliant to JEDEC standard for SSTUB32868
I
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2
×
SSTUA32864 or 2
×
SSTUA32866)
I
Parity checking function across 22 input data bits
I
Parity out signal
I
Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
I
Meets or exceeds SSTUB32868 JEDEC standard speed performance
I
Supports up to 450 MHz clock frequency of operation
I
Permanently configured for high output drive
I
Optimized pinout for high-density DDR2 module design
I
Chip-selects minimize power consumption by gating data outputs from changing state
NXP Semiconductors
SSTUM32868
1.8 V DDR2-800 configurable registered buffer with parity
I
I
I
I
Two additional chip select inputs allow optional flexible enabling and disabling
Supports Stub Series Terminated Logic SSTL_18 data inputs
Differential clock (CK and CK) inputs
Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
I
Single 1.8 V supply operation (1.7 V to 2.0 V)
I
Available in 176-ball 6 mm
×
15 mm, 0.65 mm ball pitch TFBGA package
3. Applications
I
400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs
I
DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality
4. Ordering information
Table 1.
Ordering information
Solder process
Package
Name
SSTUM32868ET/G
SSTUM32868ET/S
Description
Version
Type number
Pb-free (SnAgCu solder ball TFBGA176 plastic thin fine-pitch ball grid array package; SOT932-1
compound)
176 balls; body 6
×
15
×
0.7 mm
Pb-free (SnAgCu solder ball TFBGA176 plastic thin fine-pitch ball grid array package; SOT932-1
compound)
176 balls; body 6
×
15
×
0.7 mm
4.1 Ordering options
Table 2.
Ordering options
Temperature range
T
amb
= 0
°C
to +70
°C
T
amb
= 0
°C
to +85
°C
Type number
SSTUM32868ET/G
SSTUM32868ET/S
SSTUM32868_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 March 2007
2 of 30
NXP Semiconductors
SSTUM32868
1.8 V DDR2-800 configurable registered buffer with parity
5. Functional diagram
RESET
SSTUM32868
CK
CK
VREF
DCKE0,
DCKE1
2
2
2
D
CLK
R
Q
2
QCKE0A,
QCKE1A
QCKE0B,
QCKE1B
2
DODT0,
DODT1
2
2
D
CLK
R
Q
2
2
QODT0A,
QODT1A
QODT0B,
QODT1B
2
DCS0
D
CLK
R
Q
QCS0A
QCS0B
CSGEN
DCS1
D
CLK
R
Q
QCS1A
QCS1B
DCS2
DCS3
one of 22 channels
D1
D CE
CLK
R
Q
Q1B
Q1A
to 21 other channels
(1)
002aac512
(1) Register A configuration (C = 0): D2 to D5, D7, D9 to D12, D17 to D28
Register B configuration (C = 1): D2 to D12, D17 to D20, D22, D24 to D28
Fig 1. Logic diagram of SSTUM32868 (positive logic)
SSTUM32868_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 March 2007
3 of 30
NXP Semiconductors
SSTUM32868
1.8 V DDR2-800 configurable registered buffer with parity
RESET
CK
CK
Dn
(1)
VREF
22
22
D
CLK
R CE
22
22
QnA
(2)
QnB
(3)
Q
22
22
PAR_IN
D
CLK
R
CE
Q
PARITY GENERATOR
AND
ERROR CHECK
QERR
DCS0
D
CLK
R
Q
QCS0A
QCS0B
CSGEN
DCS1
D
CLK
R
Q
QCS1A
QCS1B
DCS2
DCS3
002aac497
(1) Register A configuration (C = 0): D1 to D5, D7, D9 to D12, D17 to D28
Register B configuration (C = 1): D1 to D12, D17 to D20, D22, D24 to D28
(2) Register A configuration (C = 0): Q1A to Q5A, Q7A, Q9A to Q12A, Q17A to Q28A
Register B configuration (C = 1): Q1A to Q12A, Q17A to Q20A, Q22A, Q24A to Q28A
(3) Register A configuration (C = 0): Q1B to Q5B, Q7B, Q9B to Q12B, Q17B to Q28B
Register B configuration (C = 1): Q1B to Q12B, Q17B to Q20B, Q22B, Q24B to Q28B
Fig 2. Parity logic diagram (positive logic)
SSTUM32868_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 March 2007
4 of 30
NXP Semiconductors
SSTUM32868
1.8 V DDR2-800 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUM32868ET/G
ball A1
SSTUM32868ET/S
index area
1
B
D
F
H
K
M
P
T
V
Y
A
C
E
G
J
L
N
R
U
W
2
3
4
5
6
7
8
AA
AB
002aac513
Transparent top view
Fig 3. Pin configuration for TFBGA176
SSTUM32868_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 March 2007
5 of 30
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