• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 200MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT23S08E-1 1x
– IDT23S08E-2 1x, 2x
– IDT23S08E-3 2x, 4x
– IDT23S08E-4 2x
– IDT23S08E-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V V
DD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
IDT23S08E
DESCRIPTION:
The IDT23S08E is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 200MHz.
The IDT23S08E has two banks of four outputs each that are controlled via
two select addresses. By proper selection of input addresses, both banks can
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08E enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µ A
for Industrial temperature range, and the outputs are tri-stated.
The IDT23S08E is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08E is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
FBK
REF
16
1
2
(-5)
2
PLL
3
2
CLKA1
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
(-2, -3)
2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2006
Integrated Device Technology, Inc.
MARCH 2006
DSC 6499/7
IDT23S08E
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
I
IK
(V
I
< 0)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
A
= 55°C
(in still air)
(3)
T
STG
Operating
Temperature
Operating
Temperature
Continuous Current
Maximum Power Dissipation
Storage Temperature Range
Commercial Temperature
Range
Industrial Temperature
Range
-40 to +85
°C
±100
0.7
–65 to +150
0 to +70
mA
W
°C
°C
Input Clamp Current
Continuous Output Current
Max.
–0.5 to +4.6
–0.5 to +5.5
–0.5 to
V
DD
+0.5
–50
±50
mA
mA
Unit
V
V
V
V
I (2)
V
I
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
SOIC/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Number
REF
(1)
CLKA1
(2)
CLKA2
(2)
V
DD
GND
CLKB1
(2)
CLKB2
(2)
S2
(3)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
Functional Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
S1
(3)
CLKB3
(2)
CLKB4
(2)
GND
V
DD
CLKA3
(2)
CLKA4
(2)
FBK
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
IDT23S08E
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(1)
SELECT INPUT DECODING
S2
L
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
S1
L
H
L
H
CLK A
Tri-State
Driven
Driven
Driven
CLK B
Tri-State
Tri-State
Driven
Driven
Output Source
PLL
PLL
REF
PLL
PLL Shut Down
Y
N
Y
N
AVAILABLE OPTIONS FOR IDT23S08
Device
IDT23S08E-1
IDT23S08E-1H
IDT23S08E-2
IDT23S08E-2
IDT23S08E-2H
(1)
IDT23S08E-2H
(1)
IDT23S08E-3
(1)
IDT23S08E-3
(1)
IDT23S08E-4
IDT23S08E-5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 x Reference
Reference
2 x Reference
2 x Reference
4 x Reference
2 x Reference
Reference/2
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference/2
Reference
Reference or
Reference
(2)
2 x Reference
2 x Reference
Reference/2
NOTES:
1. Contact factory for availability.
2. Output phase is indeterminant (0° or 180° from input clock).
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
3
IDT23S08E
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT23S08E, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
OPERATING CONDITIONS- COMMERCIAL
Symbol
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance below 100MHz
Load Capacitance from 100MHz to 200MHz
Input Capacitance
(1)
Parameter
Test Conditions
Min.
3
0
—
—
—
Max.
3.6
70
30
15
7
Unit
V
°
C
pF
pF
pF
NOTE:
1. Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD_PD
Parameter
Input LOW Voltage Level
Input HIGH Voltage Level
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Power Down Current
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (-1, -2, -3, -4)
I
OL
= 12mA (-1H, -2H, -5H)
I
OH
= -8mA (-1, -2, -3, -4)
I
OH
= -12mA (-1H, -2H, -5H)
REF = 0MHz (S2 = S1 = H)
100MHz CLKA (-1, -2, -3, -4)
100MHz CLKA (-1H, -2H, -5H)
I
DD
Supply Current
Unloaded Outputs
Select Inputs at V
DD
or GND
66MHz CLKA (-1, -2, -3, -4)
66MHz CLKA (-1H, -2H, -5H)
33MHz CLKA (-1, -2, -3, -4)
33MHz CLKA (-1H, -2H, -5H)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12
45
70
32
50
18
30
mA
µA
2.4
—
—
V
Conditions
Min.
—
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
0.8
—
50
100
0.4
Unit
V
V
µA
µA
V
4
IDT23S08E
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS - COMMERCIAL
Symbol
t
1
t
1
t
1
Parameter
Output Frequency
Output Frequency
Output Frequency
Duty Cycle = t
2
÷
t
1
(-1, -2, -3, -4, -1H, -2H, -5H)
Duty Cycle = t
2
÷
t
1
(-1, -2, -3, -4, -1H, -2H, -5H)
t
3
t
3
t
3
t
4
t
4
t
4
t
5
Rise Time (-1, -2, -3, -4)
Rise Time (-1, -2, -3, -4)
Rise Time (-1H, -2H, -5H)
Fall Time (-1, -2, -3, -4)
Fall Time (-1, -2, -3, -4)
Fall Time (-1H, -5H)
Output to Output Skew on same Bank
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H, -5H)
Output Bank A to Output Bank B (-1, -4, -2H, -5H)
Output Bank A to Output Bank B Skew (-2, -3)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to FBK Rising Edge
Device to Device Skew
Output Slew Rate
Cycle to Cycle Jitter
(-1, -1H, -4, -5H)
tJ
Conditions
30pF Load, all devices
20pF Load, -1H, -2H, -5H Devices
(1)
15pF Load, -1, -2, -3, -4 devices
Measured at 1.4V, F
OUT
= 66.66MHz
30pF Load
Measured at 1.4V, F
OUT
= 50MHz
15pF Load
Measured between 0.8V and 2V, 30pF Load
Measured between 0.8V and 2V, 15pF Load
Measured between 0.8V and 2V, 30pF Load
Measured between 0.8V and 2V, 30pF Load
Measured between 0.8V and 2V, 15pF Load
Measured between 0.8V and 2V, 30pF Load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of devices
Measured between 0.8V and 2V on -1H, -2H, -5H
device using Test Circuit 2
Measured at 66.67 MHz, loaded outputs, 15pF Load
Measured at 66.67 MHz, loaded outputs, 30pF Load
Measured at 133.3 MHz, loaded outputs, 15pF Load
Measured at 66.67 MHz, loaded outputs, 30pF Load
Measured at 66.67 MHz, loaded outputs, 15pF Load
Stable Power Supply, valid clocks presented
on REF and FBK pins
Min.
10
10
10
40
45
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
Typ.
—
—
—
50
50
—
—
—
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
Max.
100
200
200
60
55
2.2
1.5
1.5
2.2
1.5
1.25
200
200
200
400
±250
700
—
200
200
100
400
400
1
Unit
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ms
Cycle to Cycle Jitter
(-2, -2H, -3)
PLL Lock Time
t
LOCK
NOTE:
1. IDT23S08E-5H has maximum input frequency of 200MHz and maximum output of 100MHz.
Two workers were installing a light bulb. One was standing on the other's shoulders. After a long time, the worker below didn't see any movement from above, so he asked the worker above: "Hey, is it i...
CE6.0 uses RDP6.0, which has a problem of double authentication when connecting to the remote desktop. Does anyone have a good way to achieve a one-time authentication method like RDP5.5?...
I just installed CCS v5, but there is an error when compiling the program. I am very depressed. I don't know what the problem is. It has been two days! Can you help me find out what the problem is? He...
Abstract : This paper introduces the method and example of external memory expansion of USB interface microcontroller SL11R, and tests the working speed of external SRAM and EDO DRAM.Keywords : MCU SL...
International Solar Photovoltaic Network News: Chinese inverter company Sungrow announced that it will build a 3GW photovoltaic inverter manufacturing plant in Bangalore, the capital of Karnataka, ...[Details]
In the war without gunpowder between China and the United States,
ZTE
has become a new victim. The seven-year chip ban by the United States has pushed this communications giant to a life-or...[Details]
For 80,000
ZTE
(000063.SZ) employees and more Chinese ICT (information and communication technology) industry practitioners, the news from across the ocean on the evening of April 16 kept t...[Details]
1. Test conditions Hardware: STM32L432KC Main frequency: 80MHz Compiler: IAR 8.20.1 Compiler options: High Speed no size constraints CRC generator polynomial: 0x782f 2. Test Method The softwar...[Details]
In the actual project development process, we often need to get the running time of a section of code. The usual method is to use an oscilloscope to measure it. This blog post will use SysTick to acc...[Details]
After searching a lot of information, I finally understood the time base timer. I did not use any library functions but operated the registers directly. The following introduces the systick in STM32...[Details]
LAN8720 configuration: IP: 192.168.192.30 Gateway: 192.168.192.1 A high frequency of ARP packets is detected The content of the packet asks for the mac address of 192.168.192.1, and asks the resp...[Details]
Since the first draft of the 5G
NR standard was officially launched at
the end of 2017
, the
5G
commercialization process has taken a substantial step forward. From that moment on, mo...[Details]
In the development of artificial intelligence, talent reserve is undoubtedly an important part. Artificial intelligence should be a bottom-level technology that can be deeply embedded in any indust...[Details]
ZTE was punished, and Hou Weigui, who had already retired, had to come out of retirement again and run around to mediate. Let's follow the embedded editor to learn about the relevant content.
...[Details]
China Energy Storage Network News:
The State Grid Corporation of China, this elephant, is planning to turn around and enter the emerging power service market.
The rallying cry for the tr...[Details]
Timing and protocol are two key points in digital system debugging, and they are also where logic analyzers can play their most valuable role. How can we use a logic analyzer to quickly complete wiri...[Details]
There has been a lot of news about Huawei
phones
recently
. At the
Huawei
Global Analyst Conference
on the 17th
,
Huawei
announced that it will launch
5G
phones
in the seco...[Details]
The application of millimeter wave technology in mobile communications also involves a series of technical problems, including the large propagation loss of millimeter waves and the susceptibility ...[Details]
Talking
京公网安备 11010802033920号
EEWORLD
