CSPT857CNL8 datasheet, PDF - EEWORLD Datasheet

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CSPT857CNL8: DescriptionClock Driver, PQCC40; Categorylogic logic; File Size135KB，15 Pages; ManufacturerIDT (Integrated Device Technology)

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CSPT857CNL8 Overview

Clock Driver, PQCC40

CSPT857CNL8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
package instruction	QCCN, LCC40,.24SQ,20
Reach Compliance Code	unknown
JESD-30 code	S-PQCC-N40
JESD-609 code	e0
MaximumI(ol)	0.012 A
Humidity sensitivity level	3
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCN
Encapsulate equivalent code	LCC40,.24SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	2.5 V
Certification status	Not Qualified
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD

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IDTCSPT857C

2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2.5V - 2.6V PHASE LOCKED

LOOP DIFFERENTIAL 1:10

SDRAM CLOCK DRIVER

FEATURES:

DESCRIPTION:

IDTCSPT857C

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR (Double Data Rate)

SDRAM applications

• Operating frequency: 60MHz to 220MHz

• Very low skew:

– <100ps for PC1600 - PC2700

– <75ps for PC3200

• Very low jitter:

– <75ps for PC1600 - PC2700

– <50ps for PC3200

• 2.5V AV

and 2.5V V

DDQ

for PC1600-PC2700

• 2.6V AV

and 2.6V V

DDQ

for PC3200

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-

pin VFBGA packages

The CSPT857C is a PLL based clock driver that acts as a zero delay buffer

to distribute one differential clock input pair(CLK,

CLK

) to 10 differential output

pairs (Y

[0:9]

, Y

[0:9]

) and one differential pair of feedback clock output (FBOUT,

FBOUT).

External feedback pins (FBIN,

FBIN)

for synchronization of the

outputs to the input reference is provided. A CMOS Enable/Disable pin is

available for low power disable. When the input frequency falls below

approximately 20MHz, the device will enter power down mode. In this mode,

the receivers are disabled, the PLL is turned off, and the output clock drivers

are tristated, resulting in a current consumption of less than 200µA.

The CSPT857C requires no external components and has been optimised

for very low I/O phase error, skew, and jitter, while maintaining frequency and

duty cycle over the operating voltage and temperature range. The CSPT857C,

designed for use in both module assemblies and system motherboard based

solutions, provides an optimum high-performance clock source.

The CSPT857C is available in Commercial Temperature Range (0°C to

+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering

Information for details.

APPLICATIONS:

• Meets or exceeds JEDEC standard JESD 82-1A for registered

DDR clock driver

• Meets proposed DDR1-400 specification

• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),

PC2700 (DDR333), PC3200 (DDR400)

• Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,

SSTVF16859, DDR1 register, provides complete solution for

DDR1 DIMMs

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2003

Integrated Device Technology, Inc.

JUNE 2003

DSC-6201/13

CSPT857CNL8 Related Products

	CSPT857CNL8	CSPT857CNL	99M007-000/20	CSPT857CBVI8	CSPT857CPA
Description	Clock Driver, PQCC40	PLL Based Clock Driver, 857 Series, 10 True Output(s), 0 Inverted Output(s), PLASTIC, VFQFPN-40	Training Kit	Clock Driver, PBGA56	PLL Based Clock Driver, 857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-48
Is it Rohs certified?	incompatible	incompatible	-	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	QCCN, LCC40,.24SQ,20	HVQCCN, LCC40,.24SQ,20	-	-	TSSOP, TSSOP48,.3,20
Reach Compliance Code	unknown	not_compliant	-	unknown	not_compliant
JESD-30 code	S-PQCC-N40	S-XQCC-N40	-	R-PBGA-B56	R-PDSO-G48
JESD-609 code	e0	e0	-	e0	e0
MaximumI(ol)	0.012 A	0.012 A	-	0.012 A	0.012 A
Humidity sensitivity level	3	3	-	-	1
Number of terminals	40	40	-	56	48
Maximum operating temperature	70 °C	70 °C	-	85 °C	70 °C
Package body material	PLASTIC/EPOXY	UNSPECIFIED	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCN	HVQCCN	-	FBGA	TSSOP
Encapsulate equivalent code	LCC40,.24SQ,20	LCC40,.24SQ,20	-	BGA56,6X10,25	TSSOP48,.3,20
Package shape	SQUARE	SQUARE	-	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	GRID ARRAY, FINE PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	2.5 V	2.5 V	-	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Nominal supply voltage (Vsup)	2.5 V	2.5 V	-	2.5 V	2.5 V
surface mount	YES	YES	-	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	-	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD	NO LEAD	-	BALL	GULL WING
Terminal pitch	0.5 mm	0.5 mm	-	0.635 mm	0.5 mm
Terminal location	QUAD	QUAD	-	BOTTOM	DUAL

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