LP21-SR-27.0M-30E1GH datasheet, PDF

Datasheet> All Categories > Passive components> Crystal/resonator> LP21-SR-27.0M-30E1GH

LP21-SR-27.0M-30E1GH: DescriptionSeries - Fundamental Quartz Crystal, 27MHz Nom, ROHS COMPLIANT PACKAGE-2; CategoryPassive components Crystal/resonator; File Size92KB，6 Pages; ManufacturerPletronics; Environmental Compliance

Download Datasheet Parametric View All

LP21-SR-27.0M-30E1GH Overview

Series - Fundamental Quartz Crystal, 27MHz Nom, ROHS COMPLIANT PACKAGE-2

LP21-SR-27.0M-30E1GH Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Pletronics
package instruction	ROHS COMPLIANT PACKAGE-2
Reach Compliance Code	compliant
Other features	AT-CUT CRYSTAL; BULK
Ageing	5 PPM/YEAR
Crystal/Resonator Type	SERIES - FUNDAMENTAL
Drive level	1000 µW
frequency stability	0.0015%
frequency tolerance	30 ppm
JESD-609 code	e3
Manufacturer's serial number	LP21
Installation features	THROUGH HOLE MOUNT
Nominal operating frequency	27 MHz
Maximum operating temperature	75 °C
Minimum operating temperature	-20 °C
physical size	L10.8XB4.47XH2.1 (mm)/L0.425XB0.176XH0.083 (inch)
Series resistance	40 Ω
surface mount	NO
Terminal surface	Matte Tin (Sn)

Preview

Download Datasheet

View All

LP21 / LP24 / LP49 Series

Low Profile Crystal

February 2010

• The Pletronics’ LP49 Series is a low profile

thru-hole crystal

• Bulk packaging

• 3 MHz to 70 MHz

• HC-49/US

• AT Cut Crystal

LP21 0.082 (2.10mm) high

LP24 0.100 (2.50mm) high

LP49 0.140 (3.56mm) high

Pletronics Inc. certifies this device is in accordance with the

RoHS (2002/95/EC) and WEEE (2002/96/EC) directives.

Pletronics Inc. guarantees the device does not contain the following:

Cadmium, Hexavalent Chromium, Lead (<1000 ppm), Mercury, PBB’s, PBDE’s

Weight of the Device: 0.62 grams

Moisture Sensitivity Level: 1 As defined in J-STD-020C

Second Level Interconnect code: e1, e2 or e3

Electrical Specification:

Item

Frequency Range

Calibration Frequency Tolerance

Frequency Stability over OTR

Equivalent Series Resistance

(ESR)

Min

Drive Level

Shunt Capacitance

Aging per year

Specified Temperature Range

Storage Temperature Range

(C0)

-5

-40

-55

Max

200

150

120

100

+85

+125

Unit

MHz

ppm

Ohms

ppm

Condition

AT cut

at +25

C + 3

see table on page 3 for

available options

LP49

LP49/LP24

LP49/LP24/LP21

Overtone

Fundamental

3 MHz to 4 MHz

4 MHz to 5 MHz

5 MHz to 6 MHz

6 MHz to 7 MHz

7 MHz to 9 MHz

9 MHz to 10 MHz

10 MHz to 13 MHz

13 MHz to 15 MHz

15 MHz to 27 MHz

27 MHz to 30 MHz

27 MHz to 32 MHz

32 MHz to 50 MHz

50 MHz to 70 MHz

use 10 µW for testing

Pad to Pad capacitance

at +25

C + 3

see table on page 3 for available options

Product information is current as of publication date. The product conforms

to specifications per the terms of the Pletronics limited warranty. Production

processsing does not necessarily include testing of all parameters.

Recommended Resources

A differential line driver circuit diagram

PWM inverter and UPS circuit composed of CW3524

Transistor Mixer Circuit 01

Astable circuit capable of driving two relays

Macro YPF5-4 range hood circuit diagram

Capacitive energy storage memory doorbell

Bandwidth of INA106: When INA106 processes a small signal, it amplifies it 10 times, which is normal. However, when the signal increases, the output signal becomes distorted. I don't know how to solve this problem. I hope...; yangqi123 Analog electronics

Express delivery, show your board: I am very happy to receive the board. It was sent out at 8 pm last night, but it arrived at 9.40 this morning. It was so fast. Thanks to soso and Zhihui June! They have been busy arranging the board f...; fxw451 Microcontroller MCU

A complete guide to high-efficiency LED driver design: [i=s]This post was last edited by led2015 on 2020-4-29 23:25[/i]As the cost of producing LEDs falls, they are being used in more and more applications, including handheld devices, automotive electroni...; led2015 Power technology

In a four-layer board, can the top and bottom layer components be connected to the bottom layer or power layer at the same time through vias (through holes)?: [i=s]This post was last edited by hbsimon on 2016-12-22 22:47[/i] I am designing a four-layer board. Can the top and bottom layers be connected to the middle bottom layer or power layer through vias (...; hbsimon PCB Design

Please STM32FAE must take a look at this issue: Chip model: "STM32F103C6T6A GHAAV 93 CHN841" This version of TIM4 cannot be used.But this model: "STM32F103C6T6 990VD 93 MYS 806" TIM4 function is normal. Same program, same board, change the chip and...; rgqy stm32/stm8

Failed to open the project!!!: My boss gave me an mtjp project. After I downloaded CS+ from the official website and installed it, when I opened the project, the error "Opening a project failed." [Direct Error Cause] "[b]The specif...; hpu6 Renesas Electronics MCUs

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components