5962-3826701MTX datasheet, PDF

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5962-3826701MTX: Description128K X 8 EEPROM 5V, 120 ns, CDFP32; Categorystorage storage; File Size504KB，16 Pages; ManufacturerAtmel (Microchip)

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5962-3826701MTX Overview

128K X 8 EEPROM 5V, 120 ns, CDFP32

5962-3826701MTX Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	PGA
package instruction	PGA,
Contacts	30
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Maximum access time	250 ns
Other features	AUTOMATIC WRITE; DATA RETENTION: 10 YEARS
Data retention time - minimum	10
JESD-30 code	R-CPGA-P30
JESD-609 code	e0
length	16.5 mm
memory density	1048576 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	30
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programming voltage	5 V
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	4.4 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Maximum write cycle time (tWC)	10 ms

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Features

•

Fast Read Access Time - 120 ns

•

Automatic Page Write Operation

– Internal Address and Data Latches for 128-Bytes

– Internal Control Timer

Fast Write Cycle Time

– Page Write Cycle Time - 10 ms Maximum

– 1 to 128-Byte Page Write Operation

Low Power Dissipation

– 80 mA Active Current

– 300 µA CMOS Standby Current

Hardware and Software Data Protection

DATA Polling for End of Write Detection

High Reliability CMOS Technology

– Endurance: 10

or 10

Cycles

– Data Retention: 10 Years

Single 5V

10% Supply

CMOS and TTL Compatible Inputs and Outputs

JEDEC Approved Byte-Wide Pinout

•

AT28C010 Mil

•

1-Megabit

(128K x 8)

Paged Parallel

EEPROMs

AT28C010

Military

(continued)

32 LCC

Top View

A12

A15

A16

VCC

•

Pin Configuration

Pin Name

A0 - A16

I/O0 - I/O7

Function

Addresses

Chip Enable

Output Enable

Write Enable

Data Inputs/Outputs

No Connect

44 LCC

Top View

A15

A16

VCC

A14

CERDIP, FLATPACK

Top View

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

I/O0

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

I/O7

A12

A13

A11

A10

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

I/O0

A14

A13

A11

A10

I/O7

PGA

Top View

0010D–PEEPR–7/09

Description

The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Mem-

ory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with

power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is

less than 300

μA.

The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for

external components. The device contains a 128-byte page register to allow writing of up to 128-

bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally

latched, freeing the address and data bus for other operations. Following the initiation of a write

cycle, the device will automatically write the latched data using an internal control timer. The end

of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has

been detected a new access for a read or write can begin.

Atmel's 28C010 has additional features to ensure high quality and manufacturability. The device

utilizes internal error correction for extended endurance and improved data retention character-

istics. An optional software data protection mechanism is available to guard against inadvertent

writes. The device also includes an extra 128-bytes of EEPROM for device identification or

tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on OE and A9

with Respect to Ground ...................................-0.6V to +13.5V

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

AT28C010 Military

0010D–PEEPR–7/09

AT28C010 Military

Device Operation

READ:

The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is

high, the data stored at the memory location determined by the address pins is asserted on the

outputs. The outputs are put in the high impedance state when either CE or OE is high. This

dual-line control gives designers flexibility in preventing bus contention in their system.

BYTE WRITE:

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high

initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started

it will automatically time itself to completion. Once a programming operation has been initiated

and for the duration of t

, a read operation will effectively be a polling operation.

PAGE WRITE:

The page write operation of the AT28C010 allows 1 to 128-bytes of data to be

written into the device during a single internal programming period. A page write operation is ini-

tiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127

additional bytes. Each successive byte must be written within 150

μs

BLC

) of the previous byte.

If the t

BLC

limit is exceeded the AT28C010 will cease accepting data and commence the internal

programming operation. All bytes during a page write operation must reside on the same page

as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the

page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes

may be loaded in any order and may be altered within the same load period. Only bytes which

are specified for writing will be written; unnecessary cycling of other bytes within the page does

not occur.

DATA POLLING:

The AT28C010 features DATA Polling to indicate the end of a write cycle.

During a byte or page write cycle an attempted read of the last byte written will result in the com-

plement of the written data to be presented on I/O7. Once the write cycle has been completed,

true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at

anytime during the write cycle.

TOGGLE BIT:

In addition to DATA Polling the AT28C010 provides another method for determin-

ing the end of a write cycle. During the write operation, successive attempts to read data from

the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6

will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during

the write cycle.

DATA PROTECTION:

If precautions are not taken, inadvertent writes may occur during transi-

tions of the host system power supply. Atmel has incorporated both hardware and software fea-

tures that will protect the memory against inadvertent writes.

HARDWARE PROTECTION:

Hardware features protect against inadvertent writes to the

AT28C010 in the following ways: (a) V

sense - if V

is below 3.8V (typical) the write function

is inhibited; (b) V

power-on delay - once V

has reached 3.8V the device will automatically

time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE

high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the

WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION:

A software controlled data protection feature has been

implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent

inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is

shipped from Atmel with SDP disabled.

SDP is enabled by the host system issuing a series of three write commands; three specific

bytes of data are written to three specific addresses (refer to Software Data Protection Algo-

rithm). After writing the 3-byte command sequence and after t

the entire AT28C010 will be

protected against inadvertent write operations. It should be noted, that once protected the host

may still perform a byte or page write to the AT28C010. This is done by preceding the data to be

written by the same 3-byte command sequence used to enable SDP.

0010D–PEEPR–7/09

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