HY57V641620HGLT-7I datasheet, PDF

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HY57V641620HGLT-7I: DescriptionSynchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size142KB，12 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V641620HGLT-7I Overview

Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57V641620HGLT-7I Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e6
length	22.238 mm
memory density	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.194 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.16 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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HY57V641620HG-I Series

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require

low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

Note)

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

All inputs and outputs referenced to positive edge of

system clock

Data mask function by UDQM or LDQM

Internal four banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

ORDERING INFORMATION

Part No.

HY57V641620HGT-5I/55I/6I/7I

HY57V641620HGT-KI

HY57V641620HGT-HI

HY57V641620HGT-8I

HY57V641620HGT-PI

HY57V641620HGT-SI

HY57V641620HGLT-5I/55I/6I/7I

HY57V641620HGLT-KI

HY57V641620HGLT-HI

HY57V641620HGLT-8I

HY57V641620HGLT-PI

HY57V641620HGLT-SI

Clock Frequency

200/183/166/143MHz

133MHz

125MHz

100MHz

200/183/166/143MHz

133MHz

125MHz

100MHz

Power

Organization

Interface

Package

Normal

4Banks x 1Mbits

x16

LVTTL

400mil 54pin TSOP II

Low power

Note : VDD(Min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 1.0/Jan. 02

HY57V641620HGLT-7I Related Products

	HY57V641620HGLT-7I	HY57V641620HGLT-6I	HY57V641620HGLT-55I
Description	Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 4MX16, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
Maker	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	TSOP2	TSOP2	TSOP2
package instruction	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
Contacts	54	54	54
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.4 ns	5.4 ns	5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz	166 MHz	182 MHz
I/O type	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e6	e6	e6
length	22.238 mm	22.238 mm	22.238 mm
memory density	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	54	54	54
word count	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
organize	4MX16	4MX16	4MX16
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096
Maximum seat height	1.194 mm	1.194 mm	1.194 mm
self refresh	YES	YES	YES
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.002 A	0.002 A	0.002 A
Maximum slew rate	0.16 mA	0.16 mA	0.16 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm

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