HD6432353TE datasheet, PDF - EEWORLD Datasheet

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HD6432353TE: DescriptionMicrocontroller, 32-Bit, MROM, CMOS, PQFP120, PLASTIC, TQFP-120; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，767 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD6432353TE Overview

Microcontroller, 32-Bit, MROM, CMOS, PQFP120, PLASTIC, TQFP-120

HD6432353TE Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	TFQFP,
Contacts	120
Reach Compliance Code	unknown
Has ADC	YES
Address bus width	24
bit size	32
maximum clock frequency	20 MHz
DAC channel	YES
DMA channel	NO
External data bus width	16
JESD-30 code	S-PQFP-G120
length	14 mm
Number of I/O lines	95
Number of terminals	120
Maximum operating temperature	75 °C
Minimum operating temperature	-20 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
ROM programmability	MROM
Maximum seat height	1.2 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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H8S/2355 Series

H8S/2355, HD6432355, HD6472355,

H8S/2353, HD6432353

Hardware Manual

ADE-602-112A

Rev. 2.0

6/4/98

Hitachi, Ltd

MC-Setsu

Contents

Preface ....... .....................................................................................................1

Section 1 Overview ........................................................................................3

1.1 Overview ......................................................................................................................... 3

1.2 Block Diagram................................................................................................................. 7

1.3 Pin Description ................................................................................................................ 8

1.3.1 Pin Arrangement................................................................................................. 8

1.3.2 Pin Functions in Each Operating Mode ............................................................... 10

1.3.3 Pin Functions ...................................................................................................... 15

Section 2 CPU................................................................................................23

2.1 Overview ......................................................................................................................... 23

2.1.1 Features .............................................................................................................. 23

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ................................... 24

2.1.3 Differences from H8/300 CPU ............................................................................ 25

2.1.4 Differences from H8/300H CPU ......................................................................... 25

2.2 CPU Operating Modes ..................................................................................................... 26

2.3 Address Space.................................................................................................................. 31

2.4 Register Configuration ..................................................................................................... 32

2.4.1 Overview ............................................................................................................ 32

2.4.2 General Registers................................................................................................ 32

2.4.3 Control Registers ................................................................................................ 34

2.4.4 Initial Register Values ........................................................................................ 35

2.5 Data Formats.................................................................................................................... 36

2.5.1 General Register Data Formats ........................................................................... 36

2.5.2 Memory Data Formats ........................................................................................ 38

2.6 Instruction Set.................................................................................................................. 39

2.6.1 Overview ............................................................................................................ 39

2.6.2 Instructions and Addressing Modes..................................................................... 40

2.6.3 Table of Instructions Classified by Function ...................................................... 42

2.6.4 Basic Instruction Formats ................................................................................... 52

2.7 Addressing Modes and Effective Address Calculation...................................................... 53

2.7.1 Addressing Mode................................................................................................ 53

2.7.2 Effective Address Calculation............................................................................. 56

2.8 Processing States.............................................................................................................. 59

2.8.1 Overview ............................................................................................................ 59

2.8.2 Reset State.......................................................................................................... 60

2.8.3 Exception-Handling State ................................................................................... 61

2.8.4 Program Execution State..................................................................................... 64

2.8.5 Bus-Released State ............................................................................................. 64

2.8.6 Power-Down State .............................................................................................. 64

2.9 Basic Timing ................................................................................................................... 65

2.9.1 Overview ............................................................................................................ 65

2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 65

2.9.3 On-Chip Supporting Module Access Timing....................................................... 66

2.9.4 External Address Space Access Timing .............................................................. 67

Section 3 MCU Operating Modes .................................................................. 69

3.1 Overview ......................................................................................................................... 69

3.1.1 Operating Mode Selection .................................................................................. 69

3.1.2 Register Configuration........................................................................................ 70

3.2 Register Descriptions ....................................................................................................... 70

3.2.1 Mode Control Register (MDCR)......................................................................... 70

3.2.2 System Control Register (SYSCR)...................................................................... 71

3.3 Operating Mode Descriptions........................................................................................... 72

3.3.1 Mode 1 ............................................................................................................... 72

3.3.2 Mode 2 ............................................................................................................... 72

3.3.3 Mode 3 ............................................................................................................... 72

3.3.4 Mode 4 ............................................................................................................... 72

3.3.5 Mode 5 ............................................................................................................... 73

3.3.6 Mode 6 ............................................................................................................... 73

3.3.7 Mode 7 ............................................................................................................... 73

3.4 Pin Functions in Each Operating Mode ............................................................................ 74

3.5 Memory Map in Each Operating Mode ............................................................................ 74

Section 4 Exception Handling ........................................................................ 79

4.1 Overview ......................................................................................................................... 79

4.1.1 Exception Handling Types and Priority............................................................... 79

4.1.2 Exception Handling Operation............................................................................ 80

4.1.3 Exception Vector Table ...................................................................................... 80

4.2 Reset................................................................................................................................ 82

4.2.1 Overview ............................................................................................................ 82

4.2.2 Reset Types ........................................................................................................ 82

4.2.3 Reset Sequence................................................................................................... 83

4.2.4 Interrupts after Reset........................................................................................... 84

4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 84

4.3 Traces .............................................................................................................................. 84

4.4 Interrupts ......................................................................................................................... 85

4.5 Trap Instruction ............................................................................................................... 86

4.6 Stack Status after Exception Handling ............................................................................. 87

4.7 Notes on Use of the Stack ................................................................................................ 88

Section 5 Interrupt Controller.........................................................................89

5.1 Overview ......................................................................................................................... 89

5.1.1 Features .............................................................................................................. 89

5.1.2 Block Diagram.................................................................................................... 90

5.1.3 Pin Configuration................................................................................................ 90

5.1.4 Register Configuration........................................................................................ 91

5.2 Register Descriptions ....................................................................................................... 92

5.2.1 System Control Register (SYSCR)...................................................................... 92

5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 93

5.2.3 IRQ Enable Register (IER) ................................................................................. 94

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 95

5.2.5 IRQ Status Register (ISR) ................................................................................... 96

5.3 Interrupt Sources.............................................................................................................. 97

5.3.1 External Interrupts .............................................................................................. 97

5.3.2 Internal Interrupts ............................................................................................... 98

5.3.3 Interrupt Exception Handling Vector Table......................................................... 98

5.4 Interrupt Operation........................................................................................................... 102

5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 102

5.4.2 Interrupt Control Mode 0 .................................................................................... 105

5.4.3 Interrupt Control Mode 2 .................................................................................... 106

5.4.4 Interrupt Exception Handling Sequence .............................................................. 109

5.4.5 Interrupt Response Times ................................................................................... 110

5.5 Usage Notes..................................................................................................................... 111

5.5.1 Contention between Interrupt Generation and Disabling ..................................... 111

5.5.2 Instructions that Disable Interrupts...................................................................... 112

5.5.3 Times when Interrupts are Disabled .................................................................... 112

5.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... 113

5.6 DTC Activation by Interrupt ............................................................................................ 114

5.6.1 Overview ............................................................................................................ 114

5.6.2 Block Diagram.................................................................................................... 114

5.6.3 Operation............................................................................................................ 115

Section 6 Bus Controller ................................................................................117

6.1 Overview ......................................................................................................................... 117

6.1.1 Features .............................................................................................................. 117

6.1.2 Block Diagram.................................................................................................... 118

6.1.3 Pin Configuration................................................................................................ 119

6.1.4 Register Configuration........................................................................................ 119

6.2 Register Descriptions ....................................................................................................... 120

6.2.1 Bus Width Control Register (ABWCR)............................................................... 120

6.2.2 Access State Control Register (ASTCR) ............................................................. 121

6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 122

6.2.4 Bus Control Register H (BCRH) ......................................................................... 126

iii

HD6432353TE Related Products

	HD6432353TE	HD6432355TE	HD6472355TE	HD6432353F	HD6432355F	HD6472355F
Description	Microcontroller, 32-Bit, MROM, CMOS, PQFP120, PLASTIC, TQFP-120	Microcontroller, 32-Bit, MROM, CMOS, PQFP120, PLASTIC, TQFP-120	Microcontroller, 32-Bit, OTPROM, CMOS, PQFP120, PLASTIC, TQFP-120	Microcontroller, 32-Bit, MROM, CMOS, PQFP128, PLASTIC, QFP-128	Microcontroller, 32-Bit, MROM, CMOS, PQFP128, PLASTIC, QFP-128	Microcontroller, 32-Bit, OTPROM, CMOS, PQFP128, PLASTIC, QFP-128
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	TFQFP,	TFQFP,	TFQFP,	FQFP,	FQFP,	FQFP,
Contacts	120	120	120	128	128	128
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
Has ADC	YES	YES	YES	YES	YES	YES
Address bus width	24	24	24	24	24	24
bit size	32	32	32	32	32	32
maximum clock frequency	20 MHz	20 MHz	20 MHz	20 MHz	20 MHz	20 MHz
DAC channel	YES	YES	YES	YES	YES	YES
DMA channel	NO	NO	NO	NO	NO	NO
External data bus width	16	16	16	16	16	16
JESD-30 code	S-PQFP-G120	S-PQFP-G120	S-PQFP-G120	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128
length	14 mm	14 mm	14 mm	20 mm	20 mm	20 mm
Number of I/O lines	95	95	95	95	95	95
Number of terminals	120	120	120	128	128	128
Maximum operating temperature	75 °C	75 °C	75 °C	75 °C	75 °C	75 °C
Minimum operating temperature	-20 °C	-20 °C	-20 °C	-20 °C	-20 °C	-20 °C
PWM channel	YES	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFQFP	TFQFP	TFQFP	FQFP	FQFP	FQFP
Package shape	SQUARE	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
ROM programmability	MROM	MROM	OTPROM	MROM	MROM	OTPROM
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	3.15 mm	3.15 mm	3.15 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.4 mm	0.4 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER
Maker	Hitachi （Renesas ）	-	-	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）

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