= 10 nF; all specifications T to T unless otherwise noted.)
CC
REFIN
MIN
MAX
5%; AGND = DGND = O V;
Parameter
DC ACCURACY
Resolution
2
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Error Match
Plus or Minus Full-Scale Error
Plus or Minus Full-Scale Error Match
ANALOG INPUTS
Input Voltage Range
All Inputs
Input Current
REFERENCE INPUT
REFIN
REFIN Input Current
REFERENCE OUTPUT
REFOUT
DC Output Impedance
Reference Load Change
Short Circuit Current
3
LOGIC OUTPUTS
DB0–DB9,
BUSY/INT
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Capacitance
3
ADC Output Coding
LOGIC INPUTS
DB0–DB9,
CS, WR, RD,
CLKIN
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Leakage Current
Input Capacitance
3
CONVERSION TIMING
Acquisition Time
Single Conversion
Double Conversion
t
CLKIN
t
CLKIN
High
t
CLKIN
Low
POWER REQUIREMENTS
V
CC
Range
I
CC
, Normal Mode
I
CC
, Power-Down Mode
Power-Up Time to Operational
Specifications
DYNAMIC PERFORMANCE
Signal to Noise and Distortion
S/(N+D) Ratio
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
Channel-to-Channel Isolation
A Versions
1
10
±
1
±
1
±
12
10
±
12
10
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Conditions/Comments
See Terminology
No Missing Codes; See Terminology
See Terminology
Between Channels, AD7777/AD7778 Only; See Terminology
See Terminology
Between Channels, AD7777/AD7778 Only; See Terminology
V
BIAS
±
V
SWING
+200
1.9/2.1
+200
1.9/2.1
5
±
2
±
5
20
V min/V max
µA
max
V min/V max
µA
max
V min/V max
Ω
typ
mV max
mV max
mA max
V
IN
= V
BIAS
±
V
SWING
; Any Channel
For Specified Performance
Nominal REFOUT = 2.0 V
For Reference Load Current Change of 0 to
±
500
µA
For Reference Load Current Change of 0 to
±
1 mA
Reference Load Should Not Change During Conversion
See Terminology
0.4
4.0
±
10
10
Twos Complement
V max
V min
µA
max
pF max
I
SINK
= 1.6 mA
I
SOURCE
= 200
µA
0.8
2.4
10
10
4.5 t
CLKIN
5.5 t
CLKIN
+ 70
14 t
CLKIN
28 t
CLKIN
125/500
50
40
4.75/5.25
15
1.5
500
V max
V min
µA
max
pF max
ns min
ns max
ns max
ns max
ns min/ns max
ns min
ns min
V min/V max
mA max
mA max
µs
max
See Terminology
Period of Input Clock CLKIN
Minimum High Time for CLKIN
Minimum Low Time for CLKIN
For Specified Performance
CS
=
RD
= +5 V, CR8 = 0
CR8 = 1. All Linear Circuitry OFF
From Power-Down Mode
See Terminology
–56
–60
–75
–90
dB min
dB min
dB typ
dB typ
V
IN
= 99.88 kHz Full-Scale Sine Wave with f
SAMPLING
= 380.95 kHz
V
IN
= 99.88 kHz Full-Scale Sine Wave with f
SAMPLING
= 380.95 kHz
fa = 103.2 kHz, fb = 96.5 kHz with f
SAMPLING
= 380.95 kHz. Both
Signals Are Sine Waves at Half-Scale Amplitude
V
IN
= 100 kHz Full-Scale Sine Wave with f
SAMPLING
= 380.95 kHz
NOTES
1
Temperature range as follows: A = –40°C to +85°C.
2
1 LSB = (2
×
V
SWING
)/1024 = 1.95 mV for V
SWING
= 1.0 V.
3
Guaranteed by design, not production tested.
Specifications subject to change without notice.
–2–
REV. A
AD7776/AD7777/AD7778
TIMING SPECIFICATIONS
1, 2
(V
Parameter
INTERFACE TIMING
CS
Falling Edge to
WR
or
RD
Falling Edge
WR
or
RD
Rising Edge to
CS
Rising Edge
WR
Pulsewidth
CS
or
RD
Active to Valid Data
3, 4
Bus Relinquish Time after
RD
3, 5
Data Valid to
WR
Rising Edge
Data Valid after
WR
Rising Edge
WR
Rising Edge to
BUSY
Falling Edge
WR
Rising Edge to
BUSY
Rising Edge or
INT
Falling Edge
WR
or
RD
Falling Edge to
INT
Rising Edge
CC
= +5 V
Label
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
5%; AGND = DGND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
to T
MAX
Unit
0
0
53
60
10
45
55
10
1.5 t
CLKIN
2.5 t
CLKIN
+ 70
19.5 t
CLKIN
+ 70
33.5 t
CLKIN
+ 70
60
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns max
ns max
ns max
Test Conditions/Comments
Timed from Whichever Occurs Last
CR9 = 0
t
9
t
10
t
11
Single Conversion, CR6 = 0
Double Conversion, CR6 = 1
CR9 = 1
NOTES
1
See Figures 1 to 3.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
100% production tested. All other times are guaranteed by design, not production tested.
4
t
4
is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5
t
5
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t
5
quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
FIRST
CONVERSION
FINISHED
(CR6 = 0)
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
t
3
WR, RD
t
1
CS
t
2
BUSY
(CR8 = 0)
t
8
t
9
RD
t
11
t
4
t
5
INT
(CR8 = 1)
t
10
t
9
DB0–DB9
t
10
Figure 1. Read Cycle Timing
t
1
CS
Figure 3.
BUSY
/
INT
Timing
I
OL
1.6mA
t
2
t
3
WR
DB n
+2.1V
C
OUT
100pF
I
OH
200µA
t
6
DB0–DB9
t
7
Figure 2. Write Cycle Timing
Figure 4. Load Circuit for Bus Timing Characteristics
REV. A
–3–
AD7776/AD7777/AD7778
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
CC
to AGND or DGND . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
AGND, RTN to DGND . . . . . . . . . . . . . –0.3 V, V
CC
+ 0.3 V
CS, RD, WR,
CLKIN, DB0–DB9,
BUSY/INT
to DGND . . . . . . . . . . . . . –0.3 V, V
CC
+ 0.3 V
Analog Input Voltage to AGND . . . . . . . –0.3 V, V
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