a
DSP Microcompute
ADSP-2171/ADSP-2172/ADSP-2173
FUNCTIONAL BLOCK DIAGRAM
PROGRAM
ROM
8K x 24
PROGRAM
SEQUENCER
PROGRAM
RAM
2K x 24
MEMORY
POWERDOWN
CONTROL
LOGIC
FLAGS
DATA
ADDRESS
GENERATORS
DAG 1
DAG 2
FEATURES
30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V
ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipula-
tion Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
2K Words of On-Chip Program Memory RAM
2K Words of On-Chip Data Memory RAM
8K Words of On-Chip Program Memory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 mW Typical Power Dissipation at 5.0 V at 30 ns
70 mW Typical Power Dissipation at 3.3 V at 50 ns
Powerdown Mode Featuring Less than 0.55 mW (ADSP-
2171/ADSP-2172) or 0.36 mW (ADSP-2173) CMOS
Standby Power Dissipation with 100 Cycle Recovery
from Powerdown
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
GENERAL DESCRIPTION
DATA
MEMORY
2K x 16
PROGRAM MEMORY ADDRESS
EXTERN
ADDRES
BUS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
TIMER
SERIAL PORTS
SPORT 0
SPORT 1
EXTERN
DATA
BUS
HOST
INTERFACE
PORT
ADSP-2100 BASE
ARCHITECTURE
The ADSP-217x combines the ADSP-2100 base architecture
(three computational units, data address generators, and a pro
gram sequencer) with two serial ports, a host interface port, a
programmable timer, extensive interrupt capabilities, and on-
chip program and data memory.
In addition, the ADSP-217x supports new instructions, which
include bit manipulations–bit set, bit clear, bit toggle, bit test–
new ALU constants, new multiplication instruction (x squared
biased rounding, and global interrupt masking, for increased
flexibility. The ADSP-217x also has a Bus Grant Hang Logic
(BGH) feature.
The ADSP-217x provides 2K words (24-bit) of program RAM
and 2K words (16-bit) of data memory. The ADSP-2172 pro
vides an additional 8K words (24-bit) of program ROM. Pow
down circuitry is also provided to meet the low power needs o
battery operated portable equipment. The ADSP-217x is avai
able in 128-pin TQFP and 128-pin PQFP packages.
Fabricated in a high-speed, double metal, low power, CMOS
process, the ADSP-217X operates with a 30 ns instruction cy
time. Every instruction can execute in a single processor cycle
The ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. The
ADSP-2171 and ADSP-2172 are designed for 5.0 V applica-
tions. The ADSP-2173 is designed for 3.3 V applications. The
ADSP-2172 also has 8K words (24-bit) of program ROM.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The ADSP-217x’s flexible architecture and comprehensive in
struction set allow the processor to perform multiple operatio
in parallel. In one processor cycle the ADSP-217x can:
•
generate the next program address
•
fetch the next instruction
•
perform one or two data moves
•
update one or two data address pointers
•
perform a computational operation
This takes place while the processor continues to:
•
receive and transmit data through the two serial ports
•
receive and/or transmit data through the host interface port
•
decrement timer
© Analog Devices, Inc., 1
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S
Tel: 617/329-4700
Fax: 617/326-87
ADSP-2171/ADSP-2172/ADSP-2173
Development System
Additional Information
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-217x. The System Builder provides a high-level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into
an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-217x assembly source
code. The Runtime Library includes over 100 ANSI-standard
mathematical and DSP-specific functions.
EZ-Tools, low cost, easy-to-use hardware tools, also support the
ADSP-217x.
The ADSP-217x EZ-ICE
®
Emulator aids in the hardware de-
bugging of ADSP-217x systems. The emulator consists of hard-
ware, host computer resident software, the emulator probe, and
the pin adaptor. The emulator performs a full range of emula-
tion functions including stand-alone operation or operation in
the target, setting up to 20 breakpoints, single-step or full-speed
operation in the target, examining and altering registers and
memory values, and PC upload/download functions. If you plan
to use the emulator, you should consider the emulator’s restric-
tions (differences between emulator and processor operation).
The EZ-LAB Evaluation Board is a PC plug-in card, but it can
operate in stand-alone mode. The evaluation board/system de-
velopment board executes EPROM-based or downloaded pro-
grams. Modular Analog Front End daughter cards with different
codecs will be made available.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
®
This data sheet provides a general overview of ADSP-217x
functionality. For additional information on the architecture and
instruction set of the processor, refer to the
ADSP-2100 Family
User’s Manual.
For more information about the Development
System and ADSP-217x programmer’s reference information,
refer to the
ADSP-2100 Family Assembler Tools & Simulator
Manual.
ARCHITECTURE OVERVIEW
Figure 1 is an overall block diagram of the ADSP-217x. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-217x executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PROGRAM ROM
8K X 24
PROGRAM SRAM
2K X 24
DATA
SRAM
2K X 16
BOOT
ADDRESS
GENERATOR
POWER DOWN
CONTROL
LOGIC
3
2
PROGRAM
SEQUENCER
14
FLAGS
EXTERNAL
ADDRESS
BUS
14
PMA BUS
DMA BUS
MUX
14
24
PMD BUS
EXTERNAL
DATA
BUS
24
BUS
EXCHANGE
16
MUX
DMD BUS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
16
INPUT REGS
SHIFTER
OUTPUT REGS
CONTROL
LOGIC
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
TIMER
HIP
CONTROL
11
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
5
HIP
DATA
BUS
HIP
REGISTERS
16
R BUS
5
Figure 1. ADSP-217x Block Diagram
–2–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses.
•
Program Memory Address (PMA) Bus
•
Program Memory Data (PMD) Bus
•
Data Memory Address (DMA) Bus
•
Data Memory Data (DMD) Bus
•
Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus.
Program memory can store both instructions and data, permit-
ting the ADSP-217x to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP-
217x can fetch an operand from on-chip program memory and
the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of external buses with bus
request/grant signals (BR and
BG).
One execution mode (Go
Mode) allows the ADSP-217x to continue running from inter-
nal memory. Normal execution mode requires the processor to
halt while buses are granted.
In addition to the address and data bus for external memory
connection, the ADSP-217x has a configurable 8- or 16-bit
Host Interface Port (HIP) for easy connection to a host proces-
sor. The HIP is made up of 16 data/address pins and 11 control
pins. The HIP is extremely flexible and provides a simple inter-
face to a variety of host processors. For example, the Motorola
68000 series, the Intel 80C51 series and the Analog Devices’
ADSP-2101 can be easily connected to the HIP. The host pro-
cessor can initialize the ASDP-217x’s on-chip memory through
the HIP.
The ADSP-217x can respond to eleven interrupts. There can be
up to three external interrupts, configured as edge or level sensi-
tive, and eight internal interrupts generated by the Timer, the
Serial Ports (“SPORTs”), the HIP, the powerdown circuitry,
and software. There is also a master RESET signal.
The two serial ports provide a complete synchronous serial in-
terface with optional companding in hardware and a wide vari-
ety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable
serial clock or accept an external serial clock.
Boot circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
seven wait states are automatically generated. This allows, for
example, a 30 ns ADSP-217x to use an external 200 ns
EPROM as boot memory. Multiple programs can be selected
and loaded from the EPROM with no additional hardware. T
on-chip program memory can also be initialized through the
HIP.
The ADSP-217x features three general-purpose flag outputs
whose states can be simultaneously changed through software
You can use these outputs to signal an event to an external
device. In addition, the data input and output pins on SPORT
can be alternatively configured as an input flag and an output
flag.
A programmable interval timer generates periodic interrupts.
16-bit count register (TCOUNT) is decremented every
n
pro
cessor cycles, where
n-l
is a scaling value stored in an 8-bit reg
ter (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reload
from a 16-bit period register (TPERIOD).
The ADSP-217x instruction set provides flexible data moves
and multifunction (one or two data moves with a computation
instructions. Every instruction can be executed in a single pro
cessor cycle. The ADSP-217x assembly language uses an alge
braic syntax for ease of coding and readability. A comprehens
set of development tools supports program development.
Serial Ports
The ADSP-217x incorporates two complete synchronous seri
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-217x
SPORTs. Refer to the
ADSP-2100 Family User’s Manual
for
further details.
•
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
•
SPORTs can use an external serial clock or generate their ow
serial clock internally.
•
SPORTs have independent framing for the receive and trans
mit sections. Sections run in a frameless mode or with fram
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either o
two pulse widths and timings.
•
SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
µ-law
companding accordin
to CCITT recommendation G.711.
•
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
•
SPORTs can receive and transmit an entire circular buffer o
data with only one overhead cycle per data word. An interru
is generated after a data buffer transfer.
•
SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
•
SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. Th
internally generated serial clock may still be used in this
configuration.
REV. A
–3–
ADSP-2171/ADSP-2172/ADSP-2173
Pin Description
The ADSP-217x is available in 128-lead TQFP and 128-lead
PQFP packages. Table I contains the pin descriptions.
Table I. ADSP-217x Pin List
Pin
Group
Name
Address
Data
#
of
Input/
Pins Output Function
14
24
O
I/O
Address output for program,
data and boot memory spaces
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2
External bus request input
External bus grant output
External bus grant hang output
External program memory select
External data memory select
Boot memory select
External memory read enable
External memory write enable
Memory map select
External clock or quartz crystal
input
Processor clock output
HIP select input
HIP acknowledge output
8/16 bit host select input
0 = 16-bit; 1 = 8-bit
Boot mode select input
0 = EPROM/data bus; 1 = HIP
Bus strobe select input
0 = RD, WR; 1 = RW, DS
HIP address/data mode select
input 0 = separate; 1 =
multiplexed
HIP read strobe/read/write
select input
HIP write strobe/host data
strobe select input
HIP data/data and address
Host address 2/Address latch
enable input
Host addresses 1 and 0 inputs
Serial port 0 I/O pins (TFS0,
RFS0, DT0, DR0, SCLK0)
SPORT1
or
IRQ1
(TFS1)
IRQ0
(RFS1)
SCLK1
FO (DT1)
FI (DR1)
FL2–0
V
DD
GND
PWD
PWDACK
5
1
1
1
1
1
3
6
11
1
1
I/O
I
I
O
O
I
O
Serial port 1 I/O pins
External interrupt request #1
External interrupt request #0
Programmable clock output
Flag Output pin
Flag Input pin
General purpose flag output
pins
Power supply pins
Ground pins
Powerdown pin
Powerdown acknowledge pin
I
O
Host Interface Port
RESET
IRQ2
BR
BG
BGH
PMS
DMS
BMS
RD
WR
MMAP
CLKIN,
XTAL
CLKOUT
HSEL
HACK
HSIZE
BMODE
HMD0
HMD1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
I
I
I
O
O
O
O
O
O
O
I
I
O
I
O
The ADSP-217x host interface port is a parallel I/O port that al-
lows for an easy connection to a host processor. Through the
HIP, the ADSP-217x can be used as a memory-mapped periph-
eral to a host computer. The HIP can be thought of as an area
of dual-ported memory, or mailbox registers, that allow commu-
nication between the computational core of the ADSP-217x and
the host computer.
The HIP is completely asynchronous. The host processor can
write data into the HIP while the ADSP-217x is operating at full
speed.
The HIP can be configured with the following pins:
•
HSIZE configures HIP for 8-bit or 16-bit communication with
the host processor.
•
BMODE (when MMAP = 0) determines whether the ADSP-
217x boots from the host processor (through the HIP) or ex-
ternal EPROM (through the data bus).
•
HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
•
HMD1 selects separate address (3-bit) and data (16-bit)
buses, or a multiplexed, 16-bit address/data bus with address
latch enable.
Tying these pins to appropriate values configures the ADSP-
217x for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
In 8-bit reads, the ADSP-217x three-states the upper eight bits
of the bus. When the host processor writes an 8-bit value to the
HIP, the upper eight bits are all zeros. For additional informa-
tion refer to the
ADSP-2100 Family User’s Manual.
HIP Operation
I
I
I
HRD/HRW
HWR/HDS
HD15–0/
HAD15-0
HA2/ALE
HA1–0/
Unused
SPORT0
1
1
I
I
16
1
I/O
I
The HIP contains six data registers (HDR5–0) and two status
registers (HSR7–6) with an associated HMASK register for
masking interrupts from individual HIP data registers. All HIP
data registers are memory-mapped into the internal data
memory of the ADSP-217x. HIP transfers can be managed us-
ing either interrupts or a polling scheme. These registers are
shown in the section “ADSP-217x Registers.”
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-217x processor cycles.
2
5
I
I/O
–4–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
pins,
IRQ0, IRQ1
and
IRQ2. IRQ2
is always available as a dedi-
cated pin; SPORT1 may be reconfigured for
IRQ0, IRQ1,
and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are in-
ternally prioritized and individually maskable (except power-
down and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector ad-
dresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The interrupt control register, ICNTL, allows the external in-
terrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking prece-
dence or processed sequentially.
The IFC register is a write-only register used to force and clear
interrupts generated from software.
Table II. Interrupt Priority & Interrupt Vector Addresses
Source of Interrupt
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer
Interrupt Vector
Address (Hex)
0000 (Highest
Priorit
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest
Priority
On-chip stacks preserve the processor status and are automati
cally maintained during interrupt handling.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servi
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, the interrupt servicing is enable
ICNTL
4
3
2
1
0
15
14
13
12
11
10
9
IMASK
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 = enable, 0 = disable
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1 = enable, 0 = disable
1 = edge
0 = level
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
IFC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
INTERRUPT FORCE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTERRUPT CLEAR
IRQ2
SPORT0 Transmit
SPORT0 Receive
Software 1
Software 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
Figure 2. Interrupt Registers
REV. A
–5–
Microcontroller MCU
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