8XC51FX
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS
Commercial/Express
87C51FA/83C51FA/80C51FA/87C51FB/83C51FB/87C51FC/83C51FC
See Table 1 for Proliferation Options
Y
High Performance CHMOS
EPROM/ROM/CPU
12/24/33 MHz Operation
Three 16-Bit Timer/Counters
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer Capabilities
Up/Down Timer/Counter
Three Level Program Lock System
8K/16K/32K On-Chip Program Memory
256 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
Y
Y
Y
Y
32 Programmable I/O Lines
7 Interrupt Sources
Four Level Interrupt Priority
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL Compatible Logic Levels
64K External Program Memory Space
64K External Data Memory Space
MCS 51 Controller Compatible
Instruction Set
Power Saving Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
Extended Temperature Range Except
for 33 MHz Offering (
b
40 C to
a
85 C)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
MEMORY ORGANIZATION
ROM
Device
83C51FA
83C51FB
83C51FC
EPROM
Version
87C51FA
87C51FB
87C51FC
ROMLESS
Version
80C51FA
80C51FA
80C51FA
ROM/
EPROM
Bytes
8K
16K
32K
RAM
Bytes
256
256
256
These devices can address up to 64 Kbytes of external program/data memory.
The Intel 87C51FA/8XC51FB/8XC51FC is a single-chip control oriented microcontroller which is fabricated on
Intel's reliable CHMOS III-E technology. The Intel 83C51FA/80C51FA is fabricated on CHMOS III technology.
Being a member of the MCS 51 controller family, the 8XC51FA/8XC51FB/8XC51FC uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller
products. The 8XC51FA/8XC51FB/8XC51FC is an enhanced version of the 8XC52/8XC54/8XC58. Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation,
High Speed I/O and up/down counting capabilities such as motor control.
For the remainder of this document, the 8XC51FA, 8XC51FB, 8XC51FC will be referred to as the 8XC51FX,
unless information applies to a specific device.
Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT
INTEL CORPORATION, 2004
Order Number: 272322-005
July 2004
8XC51FX
Table 1. Proliferation Options
Standard
1
80C51FA
83C51FA
87C51FA
83C51FB
87C51FB
83C51FC
87C51FC
NOTES:
1
3.5
-1
3.5
-2
0.5
-24
3.5
-33
3.5
MHz
MHz
MHz
MHz
MHz
to
to
to
to
to
12
16
12
24
33
MHz; 5V
MHz; 5V
MHz; 5V
MHz; 5V
MHz; 5V
g
20%
g
20%
g
20%
g
20%
g
10%
-1
X
X
X
X
X
X
X
-2
X
X
X
X
X
X
X
-24
X
X
X
X
X
X
X
-33
X
X
X
X
X
X
X
X
X
X
X
X
X
X
272322 ±1
Figure 1. 8XC51FX Block Diagram
2
8XC51FX
PROCESS INFORMATION
The 87C51FA/8XC51FB/8XC51FC is manufactured
on P629.0, a CHMOS III-E process. Additional pro-
cess and reliability information is available in
the
Intel® Quality System Handbook:
http://developer.intel.com/design/quality/quality.htm
PACKAGES
Part
8XC51FX
Package Type
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-Pin QFP
272322– 23
PLCC
272322 – 2
DIP
*
Do not connect Reserved Pins.
272322– 24
QFP
Figure 2. Pin Connections
3
8XC51FX
In addition, Port 1 serves the functions of the follow-
ing special features of the 8XC51FX:
Port Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
T2 (External Count Input to Timer/
Counter 2), Clock Out
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
CEX0 (External I/O for Compare/
Capture Module 0)
CEX1 (External I/O
Capture Module 1)
CEX2 (External I/O
Capture Module 2)
CEX3 (External I/O
Capture Module 3)
CEX4 (External I/O
Capture Module 4)
for Compare/
for Compare/
for Compare/
for Compare/
PIN DESCRIPTIONS
V
CC
:
Supply voltage.
V
SS
:
Circuit ground.
V
SS1
:
Secondary ground (not on DIP devices or any
83C51FA/80C51FA device). Provided to reduce
ground bounce and improve power supply by-pass-
ing.
NOTE:
This pin is not a substitution for the V
SS
pin. (Con-
nection not necessary for proper operation.)
Port 0:
Port 0 is an 8-bit, open drain, bidirectional
I/O port. As an output port each pin can sink several
LS TTL inputs. Port 0 pins that have 1's written to
them float, and in that state can be used as high-im-
pedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting 1's, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are re-
quired during program verification.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the internal pull-
ups.
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the internal pull-
ups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX DPTR). In this application it
uses strong internal pullups when emitting 1's. Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the pullups.
4
8XC51FX
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
When the 8XC51FX is executing code from external
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
skipped during each access to external Data Memo-
ry.
EA/V
PP
:
External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be inter-
nally latched on reset.
EA
should be strapped to V
CC
for internal program
executions.
This pin also receives the programming supply volt-
age (V
PP
) during EPROM programming.
XTAL1:
Input to the inverting oscillator amplifier.
XTAL2:
Output from the inverting oscillator amplifi-
er.
RST:
Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice. The port pins will be driven to their reset condi-
tion when a minimum V
IH1
voltage is applied wheth-
er the oscillator is running or not. An internal pull-
down resistor permits a power-on reset with only a
capacitor connected to V
CC
.
ALE:
Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory. This pin (ALE/PROG ) is also the
program pulse input during EPROM programming for
the 87C51FX.
In normal operation ALE is emitted at a constant
rate of
the oscillator frequency, and may be used
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. However, the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction, idle mode, power down mode and ICE
mode. The ALE disable feature will be terminated by
reset. When the ALE disable feature is suspended or
terminated, the ALE pin will no longer be pulled up
weakly. Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN:
Program Store Enable is the read strobe to
external Program Memory.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155, ``Oscillators for Microcontrol-
lers.''
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and V
IH
specifications the capacitance will not ex-
ceed 20 pF.
5
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