K4D263238M
128M DDR SDRAM
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
Revision 1.3
August 2001
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.3 (Aug. 2001)
K4D263238M
Revision History
Revision 1.3 (August 2, 2001)
• Removed K4D263238M-QC40 with VDD&VDDQ=2.8V
• Changed VDD&VDDQ of K4D263238M-QC45 from 2.8V to 2.5V.
• Changed tCK(max) from 7ns to 10ns.
128M DDR SDRAM
Revision 1.2 (July 12, 2001)
• Corrected CAS latency of K4D263238M-QC45 from CL3 to CL4
• The specification for the 222MHz/250MHz is preliminary one.
Revision 1.1 (March 5, 2000)
• Added K4D263238M-QC40 with VDD&VDDQ=2.8V
• Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed.
- Changed CAS latency of K4D263238M-QC45 from CL4 to CL3.
• Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK
- 2 -
Rev. 1.3 (Aug. 2001)
K4D263238M
Revision 1.0 (December 13, 2000)
• Defined capacitance values
• Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK
128M DDR SDRAM
Revision 0.5 (December 8, 2000)
• Changed AC input level from Vref + 0.31V to Vref + 0.35V
• Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based.
•
Changed V
IN
/V
OUT
/V
DDQ
in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V.
Revision 0.4 (November 29, 2000)
- Preliminary
• Removed K4D263238M-QC40
• Several AC parameters of K4D263238M-QC45 have been changed
- Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns
- Corrected tDAL from 5tCK to 6tCK
• Several AC parameters of K4D263238M-QC50 have been changed
- Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Corrected tDAL from 5tCK to 6tCK
• Several AC parameters of K4D263238M-QC55 have been changed
- Changed tDQSQ from 0.45ns to 0.5ns. Changed tOH from tHP-0.6ns to tHP-0.5ns.
- Changed tDQSCK & tAC from 0.6ns to 0.75ns
- Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns
- Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns.
- Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK
• Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns
• Add DC Characteristics value
•
Define V
IH
(max) / V
IL
(min) as a note in Power & DC operating Condition table
• Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us.
•
Changed I
IL
,I
OL
test condition from 0V< V
IN
<V
DD
+0.3V to 0V< V
IN
<V
DD
.
Revision 0.3 (June 8, 2000)
• Removed Block Write function
Revision 0.2 (April 10, 2000)
• Separated tRCD into tRCDRD and tRCDWR
- tRCDRD: Row to Column delay for READ
- tRCDWR: Row to Column delay at WRITE
Revision 0.1 (March 16, 2000)
• Define the spec based on Vdd&Vddq=2.5V
• Maximum target frequency upto 250MHz@CL4
•
Removed Write Interrupt by Read function
Revision 0.0 (December 27, 1999) -
Target Spec
• Defined Target Specification
- 3 -
Rev. 1.3 (Aug. 2001)
K4D263238M
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V ± 5% power supply
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Write Interrupted by Read function
128M DDR SDRAM
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 222MHz
• Maximum data rate up to 444Mbps/pin
ORDERING INFORMATION
Part NO.
K4D263238M-QC45
K4D263238M-QC50
K4D263238M-QC55
K4D263238M-QC60
Max Freq.
222MHz
200MHz
183MHz
166MHz
Max Data Rate
444Mbps/pin
400Mbps/pin
366Mbps/pin
333Mbps/pin
SSTL_2
100 TQFP
Interface
Package
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to
1.8GB/s/chip.
I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 4 -
Rev. 1.3 (Aug. 2001)
K4D263238M
PIN CONFIGURATION
(Top View)
128M DDR SDRAM
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
N.C
N.C
N.C
N.C
N.C
VSSQ
RFU
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
51
50
49
48
47
46
45
44
43
A8(AP)
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VREF
DQ28
DQ27
DQ26
DQ25
DQ24
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDD
DM3
DM1
DQ9
DQ8
CKE
VSS
CK
CK
MCL
A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A11
A10
VDD
A3
A2
A1
A0
100 Pin TQFP
20 x 14
mm
2
42
41
40
39
38
37
36
35
34
33
32
31
0.65mm pin Pitch
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM0
DM2
BA0
VSS
CAS
RAS
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
DQS
DMi
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
11
DQ
0
~ DQ
31
V
DD
V
SS
V
DDQ
V
SSQ
MCL
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
′
s
Ground for DQ
′
s
Must Connect Low
VDDQ
VDD
- 5 -
Rev. 1.3 (Aug. 2001)
BA1
WE
CS