A40MX04-FPQ100IX79 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> A40MX04-FPQ100IX79

A40MX04-FPQ100IX79: DescriptionField Programmable Gate Array, 547 CLBs, 6000 Gates, CMOS, PQFP100, PLASTIC, QFP-100; CategoryProgrammable logic devices Programmable logic; File Size880KB，123 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

A40MX04-FPQ100IX79 Overview

Field Programmable Gate Array, 547 CLBs, 6000 Gates, CMOS, PQFP100, PLASTIC, QFP-100

A40MX04-FPQ100IX79 Parametric

Parameter Name	Attribute value
Maker	Microsemi
package instruction	QFP,
Reach Compliance Code	compliant
Other features	CAN ALSO BE OPERATED AT 5.0V
Combined latency of CLB-Max	3.7 ns
JESD-30 code	R-PQFP-G100
length	20 mm
Configurable number of logic blocks	547
Equivalent number of gates	6000
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	547 CLBS, 6000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	RECTANGULAR
Package form	FLATPACK
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.4 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

Preview

Download Datasheet

View All

v6.0

40MX and 42MX FPGA Families

Features

High Capacity

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

HiRel Features

•

Commercial, Industrial, Automotive, and Military

Temperature Plastic Packages

Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

QML Certification

Ceramic Devices Available to DSCC SMD

Ease of Integration

•

Mixed-Voltage Operation (5.0V or 3.3V for core and

I/Os), with PCI-Compliant I/Os

Up to 100% Resource Utilization and 100% Pin

Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

High Performance

•

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

Product Profile

Device

Capacity

System Gates

SRAM Bits

Logic Modules

Sequential

Combinatorial

Decode

Clock-to-Out

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

User I/O (maximum)

PCI

Boundary Scan Test (BST)

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

A40MX02

3,000

–

295

–

9.5 ns

–

147

–

44, 68

100

–

A40MX04

6,000

–

547

–

9.5 ns

–

273

–

44, 68, 84

100

–

A42MX09

14,000

–

348

336

–

5.6 ns

–

348

516

104

–

100, 160

100

176

–

A42MX16

24,000

–

624

608

–

6.1 ns

–

624

928

140

–

100, 160, 208

100

176

–

A42MX24

36,000

–

954

912

6.1 ns

–

954

1,410

176

Yes

160, 208

–

176

–

A42MX36

54,000

2,560

1,230

1,184

6.3 ns

1,230

1,822

202

Yes

–

208, 240

–

208, 256

272

January 2004

See the Actel website (www.actel.com) for the latest version of this datasheet.

40MX and 42MX FPGA Families

Table of Contents

40MX and 42MX FPGA Families

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18

Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

Parameter Measurement

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77

Package Pin Assignments

44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

v6.0

Recommended Resources

Pulse signal generation and display circuit c

Four-way flashing light string circuit (9)

Chandelier brightness controller circuit using thyristor

Improved circuit of vertical grinder control circuit

Telemetry alarm consisting of SX-3

Infrared remote control music socket circuit (2) (PH303A)

How to Make BFM Font: How can I make a bmf font? I can only find a font tool for making .c. Could you please give me some advice? Thank you!...; 吴通凯 Embedded System

Prize-winning quiz | Say goodbye to lengthy manual measurements and help engineers solve measurement problems: For more than 40 years, NI has developed automated test and automated measurement systems to help engineers solve the world’s toughest challenges. As part of NI’s Select Software portfolio, NI Test Wo...; EEWORLD社区 Test/Measurement

Selection of FPGA power chip: FPGA power chip selection:FAPGA power chips are generally divided into core power and IO power. How to choose the power consumption of the power chip is a science. The size of the power chip is relate...; eeleader FPGA/CPLD

Design of Natural Gas Engine Control System Based on TMS320LF2407: 1 Introduction　　In recent years, digital signal processor (DSP) chips have been widely used in automatic control, image processing, communication technology, network equipment, instrumentation and hom...; fish001 Microcontroller MCU

Is the copycatization of Chinese security products a blessing or a curse?: As the two sessions of this year are about to be held, I am reminded of the word "shanzhai" which became popular at this time last year. The word "shanzhai" was brought up in the two sessions in March...; xyh_521 Industrial Control Electronics

WINCE's memory is not recovered: I wrote an MFC program that runs under WINCE (5.0). In it, I allocated a space with new and then released it with delete, but the memory was not recovered (by looking at the system properties in the c...; wzqqz Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components