Silicon Junction FETs (Small Signal)
2SK2593
Silicon N-Channel Junction FET
For low-frequency amplification
For switching
0.4
unit: mm
1.6±0.15
0.8±0.1
0.4
q
Low noies, high gain
q
High gate to drain voltage V
GDO
q
Mini-type package, allowing downsizing of the sets and automatic
insertion through the tape/magazine packing.
1.6±0.1
1.0±0.1
0.5
1
0.5
3
2
0.45±0.1 0.3
0.75±0.15
s
Absolute Maximum Ratings
(Ta = 25°C)
Parameter
Drain to Source voltage
Gate to Drain voltage
Gate to Source voltage
Drain current
Gate current
Allowable power dissipation
Junction temperature
Storage temperature
Symbol
V
DSX
V
GDO
V
GSO
I
D
I
G
P
D
T
j
T
stg
Ratings
55
−55
−55
±30
10
125
125
−55
to +125
Unit
V
V
V
mA
mA
mW
°C
°C
1: Source
2: Drain
3: Gate
EIAJ: SC-75
SS-Mini Type Package (3-pin)
Marking Symbol (Example): 2B
s
Electrical Characteristics
(Ta = 25°C)
Parameter
Drain to Source cut-off current
Gate to Source leakage current
Gate to Drain voltage
Gate to Source cut-off voltage
Forward transfer admittance
Symbol
I
DSS*
I
GSS
V
GDS
V
GSC
| Y
fs
|
Conditions
V
DS
= 10V, V
GS
= 0
V
GS
=
−30V,
V
DS
= 0
I
G
=
−100µA,
V
DS
= 0
V
DS
= 10V, I
D
= 10µA
V
DS
= 10V, I
D
= 5mA, f = 1kHz
V
DS
= 10V, V
GS
= 0, f = 1MHz
V
DS
= 10V, V
GS
= 0, R
g
= 100kΩ
f = 100Hz
2.5
7.5
6.5
1.9
2.5
55
80
−5
min
1
typ
max
20
10
Unit
mA
nA
V
V
mS
pF
pF
dB
Input capacitance (Common Source) C
iss
Reverse transfer capacitance (Common Source) C
rss
Noise figure
NF
*
I
DSS
rank classification
Runk
I
DSS
(mA)
P
1 to 3
2BP
Q
2 to 6.5
2BQ
R
5 to 12
2BR
S
10 to 20
2BS
Marking Symbol
0 to 0.1
0.2±0.1
0.15
–0.05
+0.1
0.2
–0.05
+0.1
s
Features
1
Silicon Junction FETs (Small Signal)
P
D
Ta
150
5
Ta=25˚C
125
2SK2593
I
D
V
DS
10
Ta=25˚C
I
D
V
DS
Allowable power dissipation P
D
(mW)
4
8
Drain current I
D
(mA)
100
Drain current I
D
(mA)
V
GS
=0V
3
V
GS
=0
– 0.2V
6
– 0.2V
75
– 0.4V
4
– 0.6V
2
– 0.8V
– 1.0V
2
– 0.4V
– 0.6V
50
25
1
– 0.8V
– 1.0V
– 1.2V
0
6
0
2
4
6
8
10
12
0
0
20
40
60
80 100 120 140 160
0
0
1
2
3
4
5
Ambient temperature Ta (˚C)
Drain to source voltage V
DS
(V)
Drain to source voltage V
DS
(V)
I
D
V
GS
16
12
| Y
fs
|
V
GS
12
V
DS
=10V
Ta=25˚C
10
| Y
fs
|
I
D
Forward transfer admittance |Y
fs
| (mS)
V
DS
=10V
Ta=25˚C
10
14
Drain current I
D
(mA)
12
10
8
6
4
75˚C
2
0
0
– 0.2 – 0.4 – 0.6 – 0.8 –1.0
–1.2
Forward transfer admittance |Y
fs
| (mS)
V
DS
=10V
Ta=25˚C
8
8
I
DSS
=7.5mA
Ta=–25˚C
25˚C
6
6
4
4
2
2
0
–2.0
0
–1.6
–1.2
– 0.8
– 0.4
0
0
2
4
6
8
10
Gate to source voltage V
GS
(V)
Gate to source voltage V
GS
(V)
Drain current I
D
(mA)
C
iss
V
DS
Output capacitance (Common source) C
oss
(pF)
Input capacitance (Common source) C
iss
(pF)
16
V
GS
=0
Ta=25˚C
14
12
10
8
6
4
2
0
0
2
4
6
8
10
12
8
C
oss
V
DS
V
GS
=0
Ta=25˚C
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
C
rss
V
DS
Reverse transfer capacitance (Common source) C
rss
(pF)
8
V
GS
=0
Ta=25˚C
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
Drain to source voltage V
DS
(V)
Drain to source voltage V
DS
(V)
Drain to source voltage V
DS
(V)
2
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2001 MAR
PCB Design
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