a
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer,
Host Interface Port (ADSP-2111 Only)
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
ADSP-2111 Host Interface Port Provides Easy Interface
to 68000, 80C51, ADSP-21xx, Etc.
Automatic Booting of ADSP-2111 Program Memory
Through Host Interface Port
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
ADSP-2101, ADSP-2105, and ADSP-2115 are obsolete
GENERAL DESCRIPTION
DATA ADDRESS
GENERATORS
DAG 1
DAG 2
ADSP-2100 Family
DSP Microcomputers
ADSP-21xx
FUNCTIONAL BLOCK DIAGRAM
MEMORY
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
FLAGS
(ADSP-2111)
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0
SPORT 1
TIMER
HOST
INTERFACE
PORT
EXTERNAL
DATA
BUS
(ADSP-2111)
ADSP-2100 CORE
This data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
ADSP-2103
ADSP-2105
ADSP-2111
ADSP-2115
ADSP-2161/62/63/64
3.3 V Version of ADSP-2101
Low Cost DSP
DSP with Host Interface Port
Custom ROM-programmed DSPs
The following ADSP-2100 Family processors are
not
included
in this data sheet:
ADSP-2100A
ADSP-2165/66
DSP Microprocessor
ROM-programmed ADSP-216x processors
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
Mixed-Signal DSP Processors with
integrated on-chip A/D and D/A plus
powerdown
Speed and feature enhanced ADSP-2100
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
ADSP-21xx processor with ADSP-2171
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
ADSP-21msp5x
The ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
The ADSP-2101, ADSP-2105, and ADSP-2115 are no longer
available.
REV.
C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADSP-2171
ADSP-2181
Refer to the individual data sheet of each of these processors for
further information.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADSP-21xx
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-21xx proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-21xx can perform all of the following
operations:
•
•
Receive and transmit data via one or two serial ports
Receive and/or transmit data via the host interface port
(ADSP-2111 only)
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
The ADSP-2101, ADSP-2105, and ADSP-2115 comprise the
basic set of processors of the family. Each of these three devices
contains program and data memory RAM, an interval timer,
and one or two serial ports. The ADSP-2103 is a 3.3 volt
power supply version of the ADSP-2101; it is identical to the
ADSP-2101 in all other characteristics. Table I shows the
features of each ADSP-21xx processor.
The ADSP-2111 adds a 16-bit host interface port (HIP) to the
basic set of ADSP-21xx integrated features. The host port
provides a simple interface to host microprocessors or
microcontrollers such as the 8031, 68000, or ISA bus.
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . . 6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . 13
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Procedure for ADSP-216x ROM Processors . . . . 13
Wafer Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Differences for Older Revision Devices . . . . . . 14
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS
(ADSP-2101/2105/2115/2161/2163) . . . . . . . . . . . . . . . 17
Recommended Operating Conditions . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply Current & Power (ADSP-2101/2161/2163) . . . . . . 18
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 19
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPECIFICATIONS
(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Recommended Operating Conditions . . . . . . . . . . . . . . . . 21
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 23
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPECIFICATIONS (ADSP-2103/2162/2164) . . . . . . . . . 25
Recommended Operating Conditions . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 27
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TIMING PARAMETERS
(ADSP-2101/2105/2111/2115/2161/2163) . . . . . . . . . . . . 29
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . 36
TIMING PARAMETERS (ADSP-2103/2162/2164) . . . . 44
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PIN CONFIGURATIONS
68-Pin PGA (ADSP-2101) . . . . . . . . . . . . . . . . . . . . . . . . 51
68-Lead PLCC (ADSP-2101/2103/2105/2115/216x) . . . . 52
80-Lead PQFP (ADSP-2101/2103/2115/216x) . . . . . . . . . 53
80-Lead TQFP (ADSP-2115) . . . . . . . . . . . . . . . . . . . . . . 53
100-Pin PGA (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . 54
100-Lead PQFP (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . 55
PACKAGE OUTLINE DIMENSIONS
68-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
80-Lead PQFP, 80-Lead TQFP . . . . . . . . . . . . . . . . . . . . 58
100-Pin
PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
100-Lead PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . 61-62
–2–
REV.
C
ADSP-21xx
Table I. ADSP-21xx Processor Features
Feature
Data Memory (RAM)
Program Memory (RAM)
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Host Interface Port
Speed Grades
(Instruction Cycle Time)
10.24 MHz
(76.9 ns)
13.0 MHz
(76.9 ns)
13.824 MHz
(72.3 ns)
16.67 MHz
(60 ns)
20.0 MHz
(50 ns)
25 MHz
(40 ns)
Supply Voltage
Packages
68-Pin PGA
68-Lead PLCC
80-Lead PQFP
80-Lead TQFP
100-Pin PGA
100-Lead PQFP
Temperature Grades
K
Commercial
0°C to +70°C
B
Industrial
–40°C to +85°C
T
Extended
–55°C to +125°C
2101
1K
2K
2103
1K
2K
2105
1
2115
1
2111
1K
2K
•
•
•
–
•
•
•
•
•
•
–
–
–
–
–
–
•
•
•
•
–
•
•
–
–
–
–
–
⁄
2
K
1K
•
•
•
–
⁄
2
K
1K
5V
–
–
–
–
–
3.3 V
–
–
5V
•
•
–
–
–
–
–
5V
•
•
•
–
–
–
–
•
•
•
•
•
•
•
–
–
–
–
–
–
–
5V
•
•
–
–
–
•
•
•
–
2162
1
•
•
•
–
–
•
•
•
2161
1
•
•
–
•
•
–
2163
1
•
•
•
•
•
2164
1
Table II. ADSP-216x ROM-Programmed Processor Features
Feature
Data Memory (RAM)
Program Memory (ROM)
Program Memory (RAM)
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Supply Voltage
Speed Grades
(Instruction Cycle Time)
10.24 MHz
(97.6 ns)
16.67 MHz
(60 ns)
25 MHz
(40 ns)
Packages
68-Lead PLCC
80-Lead PQFP
Temperature Grades
K
Commercial
0°C to +70°C
B
Industrial
–40°C to +85°C
5V
•
•
•
•
•
•
•
•
–
–
⁄
2
K
8K
–
•
•
•
•
–
–
⁄
2
K
8K
–
3.3 V
•
•
•
–
⁄
2
K
4K
–
5V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
–
–
⁄
2
K
4K
–
3.3 V
•
•
•
•
REV.
C
–3–
ADSP-21xx
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table II shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
Development Tools
ARCHITECTURE OVERVIEW
Figure 1 shows a block diagram of the ADSP-21xx architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract
operations. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21xx executes looped code with zero
overhead—no explicit jump instructions are required to
maintain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
Efficient data transfer is achieved with the use of five internal
buses:
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The ADSP-21xx processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Devel-
opment Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-21xx
processors. The ANSI C compiler generates ADSP-21xx
assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. The ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators
provide an interactive instruction-level simulation with a
reconfigurable, windowed user interface. A PROM splitter
utility generates PROM programmer compatible files.
EZ-ICE
®
in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB
®
demonstration boards are complete DSP
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools
data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional Information
This data sheet provides a general overview of ADSP-21xx
processor functionality. For detailed design information on the
architecture and instruction set, refer to the
ADSP-2100 Family
User’s Manual,
available from Analog Devices.
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The
BMS, DMS,
and
PMS
signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-21xx to fetch two operands in a single cycle, one
from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR,
BG).
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
–4–
REV.
C
ADSP-21xx
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
14
PROGRAM
MEMORY
SRAM
or ROM
DATA
MEMORY
SRAM
BOOT
ADDRESS
GENERATOR
FLAGS
(ADSP-2111 Only)
3
PROGRAM
SEQUENCER
PMA BUS
TIMER
24
16
PMA BUS
14
14
DMA BUS
DMA BUS
MUX
EXTERNAL
ADDRESS
BUS
24
PMD BUS
PMD BUS
BUS
EXCHANGE
24
MUX
DMD BUS
16
DMD BUS
EXTERNAL
DATA
BUS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
INPUT REGS
SHIFTER
TRANSMIT REG
OUTPUT REGS
16
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
5
HOST
PORT
CONTROL
11
RECEIVE REG
SERIAL
PORT 0
(Not on ADSP-2105)
5
HOST
PORT
DATA
EXTERNAL
HOST PORT
BUS
16
R Bus
HOST INTERFACE PORT
(ADSP-2111 Only)
Figure 1. ADSP-21xx Block Diagram
One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-21xx processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. There is also a master
RESET
signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. The ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every
n
cycles, where
n–1
is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-21xx processors include two synchronous serial
ports (“SPORTs”) for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT0, SPORT1) except for the ADSP-2105,
which has only SPORT1.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
SCLK
RFS
TFS
DR
DT
Function
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
The ADSP-21xx serial ports offer the following capabilities:
Bidirectional—Each
SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each
SPORT can use an external serial
clock or generate its own clock internally.
REV.
C
–5–
Embedded System
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