Philips Semiconductors
Product data
16-bit I
2
C and SMBus I/O port with interrupt
PCA9555
I
2
C/SMBus applications and was developed to enhance the Philips
family of I@C I/O expanders. The improvements include higher drive
capability, 5V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power
switches, sensors, pushbuttons, LEDs, fans, etc.
The PCA9555 consist of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active high or Active
low operation) registers. The system master can enable the I/Os as
either inputs or outputs by writing to the I/O configuration bits. The
data for each Input or Output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with
the Polarity Inversion Register. All registers can be read by the
system master. Although pin to pin and I
2
C address compatible with
the PCF8575, software changes are required due to the
enhancements and are discussed in Application Note AN469.
The PCA9555 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C address and
allow up to eight devices to share the same I
2
C/SMBus. The fixed
I
2
C address of the PCA9555 is the same as the PCA9554 allowing
up to eight of these devices in any combination to share the same
I
2
C/SMBus.
FEATURES
•
Operating power supply voltage range of 2.3 V–5.5 V
•
5 V tolerant I/Os
•
Polarity inversion register
•
Active low interrupt output
•
Low stand-by current
•
Noise filter on SCL/SDA inputs
•
No glitch on power-up
•
Internal power-on reset
•
16 I/O pins which default to 16 inputs
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
•
Latch-up testing is done to JESDEC Standard JESD78 which
•
Four packages offered: SO24, SSOP24, TSSOP24, and
HVQFN24
exceeds 100 mA
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
DESCRIPTION
The PCA9555 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion for
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
24-Pin Plastic SSOP
24-Pin Plastic TSSOP
TEMPERATURE
RANGE
–40 to +85
°C
–40 to +85
°C
–40 to +85
°C
ORDER CODE
PCA9555D
PCA9555DB
PCA9555PW
TOPSIDE MARK
PCA9555D
PCA9555
PCA9555
DRAWING NUMBER
SOT137-1
SOT340-1
SOT355-1
SOT616-1
24-Pin Plastic HVQFN
–40 to +85
°C
PCA9555BS
9555
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
2002 Jul 26
2
853-2252 28672
Philips Semiconductors
Product data
16-bit I
2
C and SMBus I/O port with interrupt
PCA9555
SIMPLIFIED SCHEMATIC OF I/Os
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
D
FF
WRITE CONFIGURATION
PULSE
WRITE PULSE
C
K
Q
D
FF
I/O PIN
C
K
Q
Q2
Q
Q
Q1
100 kΩ
OUTPUT PORT
REGISTER DATA
V
DD
OUTPUT
PORT
REGISTER
INPUT PORT
REGISTER
D
FF
READ PULSE
C
K
Q
Q
V
SS
INPUT PORT
REGISTER DATA
TO INT
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
D
FF
C
K
Q
POLARITY
REGISTER DATA
Q
POLARITY
INVERSION
REGISTER
SU01473
NOTE:
At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up to V
DD
. The
input voltage may be raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either V
DD
or V
SS
.
2002 Jul 26
5
Embedded System
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