Philips Semiconductors
Product specification
32-bit bus transceiver with direction pin;
5 V tolerant; 3-state
FEATURES
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Wide supply voltage range of 1.2 to 3.6 V
•
Complies with JEDEC standard no. 8-1A
•
CMOS low power consumption
•
MULTIBYTE™ flow-trough standard pin-out architecture
•
Low inductance multiple power and ground pins for
minimum noise and ground bounce
•
Direct interface with TTL levels
•
Bus hold on data inputs (74LVCH32245A only)
•
Typical output ground bounce voltage:
V
OLP
< 0.8 V at V
CC
= 3.3 V; T
amb
= 25
°C
•
Typical output V
OH
undershoot voltage:
V
OHV
> 2 V at V
CC
= 3.3 V; T
amb
= 25
°C
•
Power-off disabled outputs, permitting live insertion
•
Plastic fine-pitch ball grid array package.
DESCRIPTION
74LVC32245A;
74LVCH32245A
The 74LVC(H)32245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices in a mixed 3.3 and 5 V environment.
The 74LVC(H)32245A is a 32-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. The 74LVC(H)32245A features two
output enable (nOE) inputs for easy cascading and two
send or receive (nDIR) inputs for direction control. nOE
controls the outputs so that the buses are effectively
isolated.
To ensure the high-impedance state during power-up or
power-down, input nOE should be tied to V
CC
through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH32245A bus hold data inputs eliminates the
need for external pull-up resistors to hold unused or
floating data inputs at a valid logic level (see Fig.2).
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
I/O
C
PD
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
PARAMETER
propagation delay
nA
n
to nB
n
; nB
n
to nA
n
input capacitance
input/output capacitance
power dissipation capacitance per
buffer
V
I
= GND to V
CC
; note 1
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
3.0
5.0
10
30
TYPICAL
ns
pF
pF
pF
UNIT
1999 Sep 01
2
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