5962-0325002VYC datasheet, PDF

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5962-0325002VYC: DescriptionField Programmable Gate Array, 2304 CLBs, 46000 Gates, CMOS, PQFP256, MQFP-256; CategoryProgrammable logic devices Programmable logic; File Size759KB，42 Pages; Manufacturere2v technologies

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5962-0325002VYC Overview

Field Programmable Gate Array, 2304 CLBs, 46000 Gates, CMOS, PQFP256, MQFP-256

5962-0325002VYC Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	QFF,
Contacts	256
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
JESD-30 code	S-PQFP-F256
length	37.085 mm
Configurable number of logic blocks	2304
Equivalent number of gates	46000
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2304 CLBS, 46000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	3.18 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	0.508 mm
Terminal location	QUAD
width	37.085 mm
Base Number Matches	1

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Features

•

SRAM based FPGA Dedicated to Space Use

•

SEE Hardened Cells (configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) Remove the

•

need for Triple Modular Redundancy (TMR)

Produced on Rad Hard 0.35µm CMOS Process

Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series

High Performance

– 46K Available ASIC gates (50% typ. routable)

– 60 MHz Internal Performance

– 20 MHz System Performance

– 30 MHz Array Multipliers

– 18 ns FreeRAM

™

access time

– Internal Tri-state Capability in Each Cell

FreeRAM

– 18432 Bits of Distributed SRAM Independent of Logic Cells

– Flexible, Single/Dual Port, Synchronous/Asynchronous 32x4 RAM blocks

8 Global Clocks and 4 Additional Dedicated PCI Clocks

– Fast, Low Skew Clock Distribution

– Programmable Rising/Falling Edge Transitions

– Distributed Clock Shutdown Capability for Low Power Management

Global Reset Option

384 PCI Compliant I/Os

– Programmable Output Drive

– Fast, Flexible Array Access Facilitates Pin Locking

Package Options

– MQFPF160

– MQFPF256

Design Software (System Designer)

– Combination of Atmel internally developed tools, and industry standard design

tools

– Fast and Efficient Synthesis

– Efficient Integration (Libraries, Interface, Full Back-annotation)

– Over 75 Automatic Component Generators Create Thousands

of Speed and Area Optimized Logic and RAM Functions

– Automatic/Interactive Multi-chip Partitioning

Supply Voltage 3.3V

AT40KFL040 is a 5V Tolerant Version

No Single Event Latch-up below a LET Threshold of 70 MeV/mg/cm2

Tested up to a Total Dose of 300 krads (Si) according to MIL STD 883 Method 1019

Quality Grades

– QML -Q and -V with SMD 5962-03250

– ESCC with 9304/008

Design Kit (AT40KEL-DK) Including:

– A Board with the RH FPGA (MQFPF160 or MQFPF256)

– A configuration memory (AT17 Atmel EEPROM)

– Design software and documentation

– ISP cable and software

Easy Migration to Atmel Gate Arrays for High Volume Production

Note:

All features and characteristics described for

AT40KEL040 in this document, also apply to the

AT40KFL040 unless specified otherwise.

•

Rad Hard

Reprogrammable

FPGAs with

FreeRAM

•

AT40KEL040

AT40KFL040

•

4155I–AERO–06/06

***

Table 1.

AT40KEL040

Device

Available ASIC Gates (50% typ. routable)

Rows x Columns

Core Cells

Registers

RAM Bits

I/O (max)

AT40KEL040

46K

48 x 48

2,304

3,056

18,432

384

Description

The AT40KEL040 is a fully PCI-compliant, SRAM-based FPGA with distributed 18 ns

programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks,

Cache Logic ability (partially or fully reconfigurable without loss of data), automatic com-

ponent generators, and 46,000 ASIC gates. I/O counts range from 129 to 384 in Aero-

space standard packages and support 3.3V.

The AT40KFL040 is a 5V tolerant version.

The AT40KEL040 is designed to quickly implement high performance, large gate count

designs through the use of synthesis and schematic-based tools used Windows

Linux

platform. Atmel’s design tools provide easy integration with industry standard

tools such as Synplicity, Modelsim and Leonardo Spectrum/Precision Synthesis. See

the IDS datasheet for other supported tools.

The AT40KEL040 can be used as a co-processor for high-speed (DSP/processor-

based) designs by implementing a variety of compute-intensive, arithmetic functions.

These include adaptive finite impulse response (FIR) filters, Fast Fourier Transforms

(FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required

for video compression and decompression, encryption, convolution and other multime-

dia applications.

The AT40KEL040 FPGA offers a patented distributed 18 ns SRAM capability where the

RAM can be used without losing logic resources. Multiple independent, synchronous or

asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be

created using Atmel’s macro generator tool.

The AT40KEL040’s patented 8-sided core cell with direct horizontal, vertical and diago-

nal cell-to-cell connections implements ultra fast array multipliers without using any bus-

ing resources. The AT40KEL040’s Cache Logic capability enables a large number of

design coefficients and variables to be implemented in a very small amount of silicon,

enabling vast improvement in system speed at much lower cost than conventional

FPGAs.

The AT40KEL040 is capable of implementing Cache Logic (Dynamic full/partial logic

reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems.

As new logic functions are required, they can be loaded into the logic cache without los-

ing the data already there or disrupting the operation of the rest of the chip; replacing or

complementing the active logic. The AT40KEL040 can act as a reconfigurable co-pro-

cessor.

The AT40KEL040 FPGA family is capable of implementing user-defined, automatically

generated, macros in multiple designs; speed and functionality are unaffected by the

macro orientation or density of the target device. This enables the fastest, most predict-

able and efficient FPGA design approach and minimizes design risk by reusing already

Fast, Flexible and

Efficient SRAM

Fast, Efficient Array and

Vector Multipliers

Cache Logic Design

Automatic Component

Generators

AT40KEL040

4155I–AERO–06/06

AT40KEL040

proven functions. The Automatic Component Generators work seamlessly with industry-

standard schematic and synthesis tools to create the fastest, most efficient designs

available.

The patented AT40KEL040 series architecture employs a symmetrical grid of small yet

powerful cells connected to a flexible busing network. Independently controlled clocks

and resets govern every column of cells. The array is surrounded by programmable I/O.

Devices offer 46,000 usable ASIC gates, and have 3,056 registers. AT40K series

FPGAs utilize a reliable 0.35µm single-poly, 4-metal CMOS process and are 100% fac-

tory-tested. Atmel’s PC- and workstation-based integrated development system (IDS) is

used to create AT40KEL040 series designs. Multiple design entry methods are sup-

ported.

The Atmel architecture was developed to provide the highest levels of performance,

functional density and design flexibility in an FPGA. The cells in the Atmel array are

small, efficient and can implement any pair of Boolean functions of (the same) three

inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays

with large numbers of cells, greatly multiplying the functionality in each cell. A simple,

high-speed busing network provides fast, efficient communication over medium and

long distances.

AT40KEL040

Configurator

Statistics extracted from configuration bitstreams show that the maximum needed size

is 1Mbit.

In order to keep the maximum number of pins assigned to signals, it is recommended to

use a serial configuration interface.

This is the reason why Atmel proposes a 1Mbit serial EEPROM for configuring the

AT40KEL040, the AT17LV010-10DP which is also a 3.3V bias chip. It is packaged into a

28-pin DIL Flat Pack 400mils wide.

This memory has been tested for total dose under bias and unbiased conditions, exhib-

iting far better results when unbiased; this is the reason why it is recommended to switch

off the memory when it is not in the configuration mode.

In addition, heavy ions tests have shown that the data stored in the memory cells are not

corrupted eventhough errors may be detected while downloading the bitstream; this is

the result of the data serialization from the parallel memory plan; therefore, it is recom-

mended to use the FPGA CRC while configuring it, and to resume the configuration

when an error is detected.

4155I–AERO–06/06

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