and XACT are registered trademarks of Xilinx. All XC-
prefix product designations, XACT-Performance, X-BLOX, XChecker,
XDM, LCA, Logic Cell, Express, VersaBlock, and VersaRing are
trademarks of Xilinx. The Programmable Logic Company and The
Programmable Gate Array Company are service marks of Xilinx.
Mentor is a registered trademark and NETED, Design Architect,
QuickSim, and QuickSim II are trademarks of Mentor Graphics, Inc.
OrCAD is a registered trademark of OrCAD Systems Corporation.
Viewlogic, Viewsim, and Viewdraw are registered trademarks of
Viewlogic Systems, Inc. Synopsys is a registered trademark of
Synopsys, Inc. Xilinx does not assume any liability arising out of the
application or use of any product described herein; nor does it convey
any license under its patents, copyrights, or maskwork rights or any
rights of others.
Xilinx reserves the right to make changes, at any time, in order to
improve reliability, function or design and to supply the best product
possible. Xilinx will not assume responsibility for the use of any circuitry
described herein other than circuitry entirely embodied in its products.
Xilinx devices and products are protected under one or more of the
R
following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557;
4,746,822; 4,750,155; 4,758,985; 4,783,607; 4,820,937; 4,821,233;
4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909;
4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603;
5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238;
5,267,187; 5,224,056; 5,245,277; 5,291,079; 5,295,090; 5,302,866;
5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220;
5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249;
5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999;
5,365,125; 5,367,207; 5,386,154; RE 34,363; RE 34,444; and
RE 34,808. Xilinx, Inc. does not represent that devices shown or
products described herein are free from patent infringement or from any
other third-party right. Xilinx assumes no obligation to correct any errors
contained herein or to advise any user of this text of any correction if
such be made. Xilinx will not assume any liability for the accuracy or
correctness of any engineering or software support or assistance
provided to a user.
Xilinx products are not intended for use in life support appliances,
devices, or systems. Use of a Xilinx product in such applications without
the written consent of the appropriate Xilinx officer is prohibited.
R
XC5200
Logic Cell Array Family
Product Description
• Fully supported by XACT
®
Development System
— Includes complete support for XACT-Performance™,
X-BLOX™, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker™
— Wide selection of PC and workstation platforms
— Interfaces to more than 100 third-party CAE tools
Preliminary (v1.0)
Features
• High-density family of Field-Programmable Gate Arrays
(FPGAs)
• Design- and process-optimized for low cost
— 0.6-µm three-layer metal (TLM) process
• System performance up to 50 MHz
• SRAM-based, in-system reprogrammable architecture
• Flexible architecture with abundant routing resources
— VersaBlock™ logic module
— VersaRing™ I/O interface
— Dedicated cell-feedthrough path
— Hierarchical interconnect structure
— Extensive registers/latches
— Dedicated carry logic for arithmetic functions
— Cascade chain for wide input functions
— Dedicated IEEE 1149.1 boundary-scan logic
— Internal 3-state bussing capability
— Four global low-skew clock or signal distribution nets
— Globally selectable CMOS or TTL input thresholds
— Output slew-rate control
— 8-mA sink current per output
• Configured by loading binary file
— Unlimited reprogrammability
— Six programming modes, including high-speed
Express™ mode
• 100% factory tested
• 100% footprint compatibility for common packages
Table 1.
Device
Typical Gate Range
VersaBlock Array
Number of CLBs
Number of Flip-Flops
Number of I/Os
TBUFs per Horizontal Longline
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for TLM
technology and 0.6-µm CMOS SRAM process, dramatic
advances have been made in silicon efficiency. These
advances position the XC5200 family as a cost-effective,
high-volume alternative to gate arrays.
Building on experiences gained with three previous
successful SRAM FPGA families, the XC5200 family
brings a robust feature set to high-density programmable
logic design. The VersaBlock logic module, the VersaRing
I/O interface, and a rich hierarchy of interconnect
resources combine to enhance design flexibility and
reduce time-to-market.
Complete support for the XC5200 family is delivered
through the familiar XACT software environment. The
XC5200 family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and
synthesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200 devices.
Initial XC5200 Field-Programmable Gate Array Family Members
XC5202
2,200 -
2,700
8x8
64
256
84
10
XC5204
3,900 -
4,800
10 x 12
120
480
124
14
XC5206
6,000 -
7,500
14 x 14
196
784
148
16
XC5210
10,000 -
12,000
18 x 18
324
1,296
196
20
XC5215
14,000 -
18,000
22 x 22
484
1,936
244
24
1
Automotive Electronics
京公网安备 11010802033920号
EEWORLD
