Micrel, Inc.
PROTOCOL TRANSPARENT
3.3V 10MHz to 729MHz
FRACTIONAL-N SYNTHESIZER
DESCRIPTION
SY87739L
SY87739L
FEATURES
■
Protocol transparent fractional-N synthesizer from
10MHz to 729MHz from a single 27MHz reference
oscillator
■
Generates exactly the correct frequency for common
transport protocols with or without FEC
■
Directly enables SY87721L CDR to lock onto any
data rate within its range
■
Exceeds BellCore and ITU jitter generation
specifications
■
Programmable via MicroWire™ interface
■
Available in 32-Pin EPAD-TQFP package
APPLICATIONS
■
■
■
■
Metro access system
Transponders
Multiplexers: access, Add Drop Mux
SONET/SDH/ATM-based transmission systems,
modules and test equipment
■
Broadband cross-connects
■
Fiber optic test equipment
■
Protocols supported:
OC-1, OC-3, OC-12, OC-48, ATM, Gigabit Ethernet,
Fast Ethernet, Fibre Channel, 2X Fibre Channel,
1394, InfiniBand, Proprietary Optical Transport
The SY87739L is a complete rate independent frequency
synthesizer integrated circuit. From a single reference
source, this device generates a differential PECL output
frequency from 10MHz up to 729MHz.
The SY87739L generates an exactly correct reference
frequency for common data transport protocols. This is
especially important in transponder applications, where a
standards compliant protocol data unit must be generated
downstream, even in the absence of any signal from the
associated upstream interface. In addition, the SY87739L
will generate exactly correct reference frequencies for
common data transport protocols augmented by forward
error correction codes. The SY87739L accepts configuration
via a MicroWire™ interface.
For proprietary applications, the SY87739L generates
reference frequencies guaranteed to enable the SY87721L
CDR to lock to any possible baud rate from 28Mbps to
2.7Gbps.
TYPICAL APPLICATIONS CIRCUIT
0.1µF
2k
31
30
TYPICAL PERFORMANCE
0.1µF
2k
26
25
FNVCF+
FNVCF-
WRVCF+
WRVCF-
Cycle-to-Cycle Jitter
vs. Frequency
6
5
22
21
V
CC
14
Saronix
SEL-2431C
27.0000MHz
7
8
3
4
REFCLK+
REFCLK-
SY87739L
CLKOUT+
CLKOUT-
RMS JITTER (ps)
4
3
2
1
0
0 100 200 300 400 500 600 700 800
OUTPUT FREQUENCY (MHz)
1
121
121
PROGCS
PROGDI
PROGSK
LOCKED
121
121
V
CC
10, 25, 32
1, 9, 17, 18, 24
6 7 8 14
Microcontroller
AnyClock and AnyRate are registered trademarks of Micrel, Inc.
MicroWire is a trademark of National Semiconductor.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
OUT
OUT
OUT
IN
1
Issue Date: November 2006
Micrel, Inc.
SY87739L
PACKAGE/ORDERING INFORMATION
GNDA
FNVCF+
FNVCF-
NC
NC
WRVCF+
WRVCF-
GNDA
Ordering Information
(1)
Part Number
24
23
22
21
20
19
18
17
VCCA
NC
CLKOUT+
CLKOUT-
NC
NC
VCCO
VCC
32 31 30 29 28 27 26 25
VCCA
NC
REFCLK+
REFCLK-
NC
PROGCS
PROGDI
PROGSK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Package
Type
H32-2
H32-2
H32-2
H32-2
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY87739LHI
SY87739LHI
SY87739LHY with
Pb-Free bar line indicator
SY87739LHY with
Pb-Free bar line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Matte-Sn
Pb-Free
Matte-Sn
Pb-Free
SY87739LHI
SY87739LHITR
(2)
SY87739LHY
SY87739LHYTR
(2, 3)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
EPAD-TQFP (H32-2)
PIN DESCRIPTION
Pin Number
1, 24
2, 5, 11, 12, 13,
15, 16, 19, 20
23, 28, 29
3, 4
Pin Name
VCCA
NC
Pin Function
Analog Supply (Power). Set to same voltage as V
CC
.
No Connect. These pins are to be left unconnected.
VCC
GND
NC
NC
NC
LOCKED
NC
NC
REFCLK±
Reference Clock Input (Differential PECL Input): This is a clock derived from an oscillator or
other sufficiently accurate frequency source. The frequency provided at this input determines,
along with the programming, the output frequency at REFOUT±. Micrel recommends using a
27.000MHz frequency source.
Program Interface Chip Select (TTL Input): This signal forms part of the MicroWire™ interface.
When active high, this signal permits the acquisition of serial data. A falling edge on this input
causes SY87739L to re-acquire lock to a new frequency, based on the program downloaded to it.
Program Interface Data In (TTL Input): One data bit is sampled on each rising edge of PRGSK,
while PROGCS is active high.
Program Interface Serial Clock (TTL Input): One bit of configuration data is read in each clock
cycle.
Supply (Power): +3.15V to +3.45V.
Ground.
Lock Output (TTL Output): This indicates proper operation of all the blocks in the clock synthesis
chain. Logic high indicates that SY87739L is generating the expected frequency at the CLKOUT±
output. Logic low indicates that one or more PLL in the clock synthesis chain has yet to achieve
proper lock.
Output Supply (Power). Set to same voltage as V
CC
.
Reference Clock Output (Differential PECL Output): This is the synthesized clock generated from
REFCLK±. It can be used to supply a reference clock to a data recovery device, such as Micrel’s
SY87721L.
Analog Ground.
Wrapper Filter (Analog I/O): These pins connect to the output from the wrapper synthesizer
charge pump, as well as the input to the corresponding VCO. A filter network, as described
below, converts the charge pump current to a voltage, and adjusts loop bandwidth.
Fractional-N Filter (Analog I/O): These pins connect to the output from the fractional-N synthesizer
charge pump, as well as the input to the corresponding Voltage Controlled Oscillator (VCO). A
filter network, as described below, converts the charge pump current to a voltage, and adjusts
loop bandwidth.
2
6
PROGCS
7
8
9, 17,
10
14
PROGDI
PROGSK
VCC
GND
LOCKED
18
21, 22
VCCO
CLKOUT±
25, 32
26, 27
GNDA
WRVCF±
30, 31
FNVCF±
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87739L
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) .................................. –0.5V to +5.0V
Input Voltage(V
IN
) ...................................... –0.5V to V
CC
ECL Output Current (I
OUT
)
Continuous ......................................................... 50mA
Surge ................................................................ 100mA
Lead Temperature (soldering, 10 sec.) ..................... 220°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Note 1.
Operating Ratings
(Note 2)
Supply Voltage (V
IN
) ............................... +3.15V to +3.45V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Junction Temperature (T
J
) ........................................ 125°C
Package Thermal Resistance
EPAD-TQFP
(θ
JA
),
(Note 3)
Still-Air .......................................................... 27.6°C/W
500lfpm ......................................................... 20.7°C/W
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng
conditions for extended periods may affect device reliability.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Measured with die attach pad soldered to PCB, JEDEC standard multi-layer board.
Note 2.
Note 3.
DC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCO
= V
CCA
= 3.3V
±5%;
GND = GNDA = 0V; T
A
= –40°C to +85°C
Symbol
V
CC
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Condition
Min
3.15
Typ
3.3
210
Max
3.45
280
Units
V
mA
PECL DC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCO
= V
CCA
= 3.3V
±5%;
GND = GNDA = 0V; T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
V
OH
V
OL
I
IL
Note 1.
Note 2.
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input LOW Current
Condition
Min
V
CC
–1.165
V
CC
–1.810
Typ
Max
V
CC
–0.880
V
CC
–1.475
V
CC
–0.830
V
CC
–1.570
Units
V
V
V
V
µA
50Ω to V
CC
–2V
50Ω to V
CC
–2V
V
IN
= V
IL
(Min.),
Note 1, 2
V
CC
–1.075
V
CC
–1.860
–1.5
The REFCLK+ pin has a nominal 75kΩ pull-down resistor connected to ground.
The RECLK– pin has a nominal 75kΩ pull-down resistor connected to ground and a nominal 75kΩ pull-up resistor connected to V
CC
.
TTL DC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCO
= V
CCA
= 3.3V
±5%;
GND = GNDA = 0V; T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OS
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input LOW Current
Output Short Circuit Current
I
OH
= –2mA
I
OL
= 4mA
V
IN
= 2.7V, V
CC
= Max.
V
IN
= V
CC
, V
CC
= Max.
V
IN
= 0.5V, V
CC
= Max.
V
OUT
= 0V, (1 sec. Max.)
–100
2.0
0.5
+20
+100
–300
–250
Condition
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
µA
µA
µA
mA
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
SY87739L
AC ELECTRICAL CHARACTERISTICS
V
CC
= V
CCO
= V
CCA
= 3.3V
±5%;
GND = GNDA = 0V; T
A
= –40°C to +85°C
Symbol
t
IRF
t
REFPWH
t
REFPWL
t
CSSK
t
SKCS
t
SKP
t
SKPWH
t
SKPWL
t
DIS
t
DIH
Parameter
REFCLK Input Rise/Fall Times
REFCLK Pulse Width High
REFCLK Pulse Width Low
PROGCS to PROGSK Preset
PROGSK to PROGCS Recovery
PROGSK Period
PROGSK Pulse Width High
PROGSK Pulse Width Low
PROGDI Data Setup
PROGDI Data Hold
CLKOUT Duty Cycle
CLKOUT Maximum Frequency
Aquisition Lock Time
Fractional-N V
CO
Operating Range
Wrapper V
CO
Operating Range
27MHz Reference Clock
t
CLKPWH
/ (t
CLKPWH
+ t
CLKPWL
)
Condition
Min
—
5
5
100
100
200
70
70
20
20
25
729
—
540
540
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
2.0
—
—
—
—
—
—
—
—
—
75
—
0.1
729
729
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
% of UI
MHz
sec
MHz
MHz
TIMING WAVEFORMS
t
REFPWH
REFCLK
t
CLKPWH
CLKOUT
t
REFPWL
t
CLKPWL
t
CSSK
PROGCS
t
SKPWH
PROGSK
PROGDI
Valid
Valid
t
SKP
t
SKPWL
t
DIS
t
DIH
t
SKCS
Valid
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
SY87739L
FUNCTIONAL DESCRIPTION
General
The SY87739L AnyClock™ Fractional-N Synthesizer is
used in serial data streaming applications, where the
incoming data rate on a channel may vary, or where the
incoming data rate on a channel is unknown ahead of time.
In these situations, a valid output stream must still be
generated even in the absence of any edges on the
corresponding input stream. Up until now, designers had to
resort to sub-optimal solutions such as providing multiple
reference oscillators. Beyond the potential noise and EMI
issues, the designer has no way to future proof his circuit,
as it would prove near impossible to pre-provision all the
reference frequencies that might be needed after
deployment, yet are unknown at this time.
The SY87739L solves this problem by generating exact
frequencies for common data streaming protocols, all from
one 27MHz reference. If any of these protocols include
overhead due to use of common digital wrappers, The
SY87739L still generates the exact frequency required,
including the overhead.
Besides generating reference rates for common protocols
directly, the SY87739L also generates reference frequencies
for Micrel’s SY87721L CDR/CMU, such that it will reliably
recover data at any rate between 28Mbps and 2,700Mbps
without any gaps.
A simple 3-wire MicroWire™ bit-serial interface loads a
configuration that describes the desired output reference
frequency. All common microcontrollers support this
MicroWire™ interface. Those microcontrollers that don’t
support this interface in hardware can easily emulate the
interface in firmware.
The large set of possible frequencies that the SY87739L
generates, are divided into three classes. First, the sets of
frequencies that match a particular data streaming protocol
are in the “protocol” category. Second, the set of frequencies
that are guaranteed to be near enough to any arbitrary data
rate such that the SY87721L will lock are in the “picket
fence” category. Third, the set of frequencies that do not fit
into either of the first two categories is in the third category,
The SY87739L generates these important reference
frequencies through two tandem PLL circuits. The first PLL
uses a modified fractional-N approach to generate a rational
ratio frequency. This PLL is capable of generating all protocol
data rates, except for those that include FEC or digital
wrapper overhead. A second, more traditional P/Q
synthesizer optionally adjusts the output frequency of the
first, fractional-N synthesizer, to accommodate these FEC
or digital wrapper data rates.
The bit serial interface conveys 32 bits of configuration
data from a microcontroller to SY87739L. This simple
interface consists of an active high chip select, a serial
clock (2MHz or less) and a serial data input. Each clock
cycle one bit of configuration data transfers to SY87739L.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
Circuit Description
The heart of SY87739L is its fractional-N synthesizer, as
shown in Figure 1.
Loop Filter
Input
Reference
Frequency
(f
REF
)
Phase-
Frequency
Detector/
Charge
Pump
VCO
Output
Frequency
(f
FNOUT
)
÷P
Mux
÷P-1
Control
Figure 1. Fractional-N Synthesizer Architecture
The two dividers in the feedback path always differ by
one count. That is, if one divider is set to divide by P = 5,
then the other divider divides by P–1 = 4 . The mux choses
between the two based on the control circuit.
The idea behind the fractional-N approach is that every
input reference edge is used. Only those output edges that
are nearest to an input edge get fed back to the phase-
frequency comparator. In addition, the nearest output edges
are chosen in such a way that the net offset, over a number
of edges, zeroes out. It is the control circuit’s job to drive
the mux such that only the “correct” edges get fed back.
In the above fractional-N circuit, if the output frequency
should be, for example, 5 times the input frequency, then P
is set to 5, and the control circuit sets the mux to only feed
back the output of the P divider.
If the output frequency should be, for example, 4
1
/
2
times
the input frequency, then the control circuit alternates evenly
between the P and the P–1 divider output. For every two
input edges (one to compare against P, and another to
compare against P–1), you will get 5 + 4 output edges,
yielding an output frequency 9/2 the input frequency.
Whereas P sets the integer part of the multiplication factor
from input to output frequency, the control circuit determines
the fractional part. By mixing the output of the P and P–1
dividers correctly, the control circuit can fashion any output
frequency from P–1 times the input to P times the input, as
long as that ratio can be expressed as a ratio of integers.
5
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