STH221
MULDEX IC FOR MULTIMEDIA TELESERVICES
HCMOS SEA OF GATE TECHNOLOGY
64 PINS QUAD FLAT PACKAGE
TWO MODES OF OPERATION: STAND-
ALONE, MICROPROCESSOR
INTERFACE FOR 8/16/32 BIT MICROPROC-
ESSORS
TRANSMITTER FUNCTIONS:
Implementation of two electrical interfaces:
- 64kbit/s only
- to 4 up to 32 Time Slot Multiplex.
Allocation of the multimedia frame structure in
B channel for 32B channels.
3 input internal multiplexer can multiplex up to
3 sources within the 64kbit/s output stream.
Serial/Parallel input to the AC data:
- Serial: using the 8th bit of the input stream.
- Parallel: using bytes provided by
microprocessor.
Serial/parallel input for the seven sub-chan-
nels.
RECEIVER FUNCTIONS:
Implementation of two electrical interfaces:
- 64kbit/s only
- to 4 up to 32 Time Slot Multiplex
Allocation of the multimedia frame structure in
Bchannel of 32 channels.
3 Output internal demultiplexer can demultiplex
up 3 signals provided by the 64kbit/s input
stream.
Serial/parallel output for AC data:
- Serial: using the 8th bit of the output stream.
- Parallel: using bytes provided by
microprocessor.
Serial/parallel output for the seven subchan-
nels.
OTHER GENERAL ASPECTS:
Interrupt procedures to access 16 input regis-
ters and 10 output registers.
Working with/without external byte synchroni-
zation depending on Protocol Select Pin and
bit programmation.
The emitter and receiver provide superframe
synchronization.
Error correction on BAS (up to two consecutive
errors can be corrected, three are detected).
Fast
receiver
synchronization
(parallel
method).
PQFP64
ORDERING NUMBER:
STH221
DESCRIPTION
The H221/Muldex integrated circuit is a multi-
plex/demultiplex for a frame structure with 8-bit
data channel. Manufactured using HCMOS ”Sea
of gates” technology, the device requires a single
5 V supply and is available in a 64 pin Quad Flat
Package. The H221/Muldex implements the
frame structure for a 64 kbit/s channe l in
audiovisual teleservices as defined by CCITT in
the H.221 recommendation with automatic gen-
eration/decoding of FAW and error correction de-
tection on BAS. It also implements the CRC4 al-
gorithm for error detection on the sub-multiframe
structure and allows the possibility of serial and/or
parallel input/output of data channels (including
the AC channel). In addition the multiframe struc-
ture is supported with automatic generation/de-
coding of the Multiframe Alignment Word and
enabling of multiframe count. The H221/Muldex is
controlled by a microprocessor using an 8-bit data
bus or can function in a stand-alone mode; stand-
ard 64 kbit/s or time division multiplex interface are
implemented.
May 1993
1/32
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STH221
PIN CONNECTION
(Top view)
Table 1:
Alphabetical Listing of Symbols.
Symbol
CDN
CONF
CP/CPI
CPI1/SYI
CPI2/IA
CPI3/IB
CPO1/SYO
CP02/OA
CP03/OB
DSN
DTACKN
Pin
41
34
60
59
58
57
47
46
45
37
36
Symbol
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DCLR
DCLT
SDO
Pin
3
4
5
6
7
8
9
10
13
19
21
Symbol
SMFR/OM
FSCR
FSCT
FSYN/CPO
IRQN
MODE/TEST
PROT
RESETN
RWN
SDI
Pin
44
12
20
48
40
24
23
26
39
11
Symbol
VSS
SMFT/IM
TDI1/TDI
TDI2
TDI3
TDO1/TDO
TDO2/RCK
TD03
VDD
CSN
Pin
1,2,28,29,53,
54
56
61
30
31
51
52
35
15,16,42,43,
62,63
25
Pin 16 must not be connected.
2/32
STH221
Table 2:
Pin Description.
Pin
3-10
11
12
13
19
20
21
23
Symbol
DB0-DB7
SDI
FSCR
DCLR
DCLT
FSCT
SDO
PROT
Mode
I/O
I
I
I
I
I
O*
I
Type
CPU
Rx
Rx
Rx
Tx
Tx
Tx
I/O Data
µP
Interface.
Serial Data Input.
Input of serial stream from line into the receiver.
64 kbit/s or 256 kbit/s up to 2048kb/sec (GCI).
Frame Syncro Rx.
Octet synchronization (if present) for the
receiver.
Data Clock Rx.
Clock of input data for receiver.
64 khz or 512 up to 4096 khz (GCI)
Data Clock Tx.
Clock of output data from transmitter.
64 khz or 512 up to 4096 khz (GCI)
Frame Syncro Tx.
Octet syncronization (if present) for the
transmitter.
Serial Data Outpu t.
Output of serial stream from
transmitter into B channel selected. Open drain in GCI mode.
Protocol select.
Select of protocol implementation:
0 = 64 kbit/s
1 = Multiplex at 512 up to 2048kb/s.
CONF = 1 Test is given by this pin.
Specific test mode of the component. In normal operation, must be
0.
CONF = 0. Selection of working mode.
MODE = 0. Controlled by CPU (CPU mode)
MODE = 1. Stand Alone (S-A Mode). mode).
Test is given by Bit 3 of Command Register.
25
CSN
I
CPU
Chip Select.
In CPU mode allows the selection of the component
by the CPU:
0 = The CPU can access internal registers using RWN, CDN,
DSN signals.
1 = The H221 is disabled.
In S-A mode this pin represents the N5 bit of the H221 protocol
(Enable/disable of the multiframe count).
Reset component.
Reset the H221 and initializes default
conditions. Low Signal = active Minimum duration = 1µs.
Tx
Terminal Data Input 2.
Serial input of data for the transmitter,
clocked by CP. Data is shifted on the falling edge of CP. Usable
only if CONF = 1 otherwise ignored.
Terminal Data Input 3.
Serial input of data for the transmitter.
Data is shifted on the falling edge of CP. Usable only if CONF = 1
otherwise ignored.
Configuration.
CONF = 0. CPI, TDI, SYI, IA, IB, IM, OM, TDO, CPO, SYO, OA,
OB, RCK, Mode pins are validated.
CONF = 1. CP, TDI 1/3, CPI 1/3, TDO 1/3, CPO 1/3, SMFT,
SMFR, TEST, FSYN pins are validated.
35
TDO 3
O
Tx
Terminal Data Output 3.
Serial Output of data received. Data is
shifted on the rising edge of CP. If CONF = 1: Open Drain else
TDO3 = 0.
Data Acknowledge.
Data acknowledge for writing from CPU and
data ready for reading.
1 = Data not yet ready or acknowledged.
0 = Data ready or acknowledged.
In S-A mode it represents the Aloc signal.
Data Strobe.
Strobe signal for data I/O from/to CPU.
0 = Data Valid on data bus.
In S-A mode it is used to strobe the BAS data on the data bus.
3/32
Function
24
MODE/
TEST
I
26
30
RESETN
TDI 2
I
I
31
TDI 3
I
Tx
34
CONF
I
36
DTCAKN
O
CPU
37
DSN
I
CPU
STH221
Table 2:
Pin Description.
Pin
39
Symbol
RWN
Mode
I
Type
CPU
Function
Read or Write.
Indicates whether the next data transfer performed
is a read or a write.
0 = Write operation.
1 = Read operation.
In S-A mode it indicates the direction of the BAS data on data bus.
Interrupt Request.
When low indicates that the H221 is
requesting interrupt service. This lead goes high when the CPU
performs the interrupt acknowledge. It is an open drain so pull-up
resistor is needed.
In S-A mode it represents the Eloc signal.
Command or Data.
Selection between the command register or
the data registers set.
0 = The CPU accesses a data register.
1 = The CPU accesses the command register.
In S-A mode it enables the computing of the CRC4 value by the
transmitter.
0 = Tx computers CRC4 value.
1 = All 1’s are transmitted on the CRC4 position (CRC4 disabled).
CONF = 1. Submultiframe received.
This signal goes high at the beginning of first bit of octet 1 of every
submultiframe. It returns low at the beginning of first bit of octet 83
of every submultiframe.
CONF = 0 Out Mask.
Frame synchronization; it goes high before the beginning of first bit
of octet 1 of every frame. It returns low between the 16th and the
72nd octet, depending on the programmed conditions. Valid only
when the receiver is frame aligned.
45
CP03/
OB
O
Rx
CONF = 1. Clock pulse for data output 3. This signal is
configurated by CPS and WIN bits. It is associated to TDO3 data.
CONF = 0. Out multiplex addr. B.
LSB of the channel number of the bit on the TDO output.
46
CP02/
OA
O
Rx
CONF = 1. Clock pulse for data output 2. This signal is
configurated by CPS and WIN bits. It is associated to TDO2 data.
CONF = 0. Out multiplex addr. A. Together with OA and SYO
indicates the channel number of the bit on the TDO output. These
signals can be used to address an external demultiplexer
separating 8 sub-channels.
47
SYO/
CPO1
O
Rx
CONF = 1. Clock pulse for data output 1. This signal is
configurated by CPS and WIN bits. It is associated to TD01 data.
CONF = 0. Synchro Output MSB of the channel number of the bit
on the TDO output. It also represents the synchronization octet;
SYO is low at the beginning of the octet.
48
FSYN/
CPO
I
-
CONF = 1. Frame Synchronization.
This 8kHz signal indicates the first bit of the first time slot for
TDO1, TDO2, TDO3, TDI1, TDI2, TDI3 multiplex.
CONF = 0 Clock Pulse Output;
Clock for the output of data from receiver. The clock input must
have a mimimum frequency of 64 KHz and a maximum frequency
of 2 MHz. Signals OA, OB and SYO have meaning only whne
CPO has a 64 KHz frequency.
40
IRQN
OD
CPU
41
CDN
I
CPU
44
SMFR/
OM
O
Rx
4/32
STH221
Table 2:
Pin Description.
Pin
51
Symbol
TDO1/
TDO
Mode
TS/O
Type
Rx
Function
CONF = 1. Terminal Output 1.
Serial output of data received. Data is shifted on the rising edge of CP.
OPEN DRAIN
CONF = 0. Terminal Data Output.
Serial output of data received, clocked by CPO. Data is shifted on
the leading edge of CPO.
CONF = 1. Terminal Output 2.
Serial output of data received.
Data is shifted on the rising edge of CP.
OPEN DRAIN
CONF = 0. Rx Clock.
A 64 KHz clock recovered by the receiver from the
incoming stream.
CONF = 1. Submultiframe transmitted.
This signal goes high at the beginning of first bit of octet 1 of every
submultiframe. It returns low at the beginning of first bit of octet 8
of every submultiframe.
CONF = 0. Input Mask.
Input Mas. Frame synch; it goes high before the transmission of the
first bit of octet # 1 of every frame. It returns low between the 16th
and the 72nd octet, depending on the programmed conditions.
CONF = 1. Clock Pulse for data input 3. This signal is configurated
by CPS and WIN bits. It is associated to TDI3 data.
CONF = 0. Input Mask.
In multiplex addr. B. LSB of the channel number of the bit on the
TDI input.
CONF = 1. Clock Pulse for data Input 2. This signal is configurated
by CPS and WIN bits. It is associated to TDI2 data.
CONF = 0. In Multiplex Addr. A
In multiplex addr. A. Together with IA and SYI indicates the
channel number of the bit on the TDI input. These signals can be
used to address the multiplexing of 8 sub-channels.
CONF = 1. Clock Pulse for data input 1. This signal is configurated
by CPS and WIN bits. It is associated to TDI1 data.
CONF = 0. Input Synchronization .Input Sync. MSB of the channel
number of the bit on the TDI input. It also represents the sync of
the outgoing octet i.e. SYI is low at the beginning of the octet.
CONF = 1. Clock Pulse.
This signal is used to generate six clock pulses: CPI1, CPI2, CPI3
and CPO1, CPO2, CPO3. Its frequency is twice binary data rate of
TDI1, TDI2, TDB and TDO1, TDO2, TDO3 multiplex.
Minimum frequency 128kHz.
Maximum frequency 4096kHz.
CONF = 0. Clock Pulse input. Clock for the input of data into
transmitter. The clock input must have a minimum frequency of
64kHz and a maximum frequency of 2 MHz. Signals IA, IB and
SYI have meaning only when CPI has a 64kHz frequency.
CONF = 1. Terminal Data Input 1.
Serial input of data for the transmitter. Data is shifted on the falling
edge of CP.
CONF = 0. Terminal Data Input. Serial input of data for the
transmitter, clocked by CPI. Data is shifted on the leading edge of
CPI.
5/32
52
TDO2/
RCK
TS/O
Rx
56
SMFT/
IM
0
Tx
57
CPI3/
IB
0
Tx
58
CPI2/
IA
0
Tx
59
CPI/
SYI
O
Tx
60
CP/CPI
I
Tx-Rx/
Tx
61
TDI1/
TDI
I
Tx
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