PSD834F2VA-15JT datasheet, PDF

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PSD834F2VA-15JT: Description256KX8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52, ROHS COMPLIANT, PLASTIC, LCC-52; CategoryThe embedded processor and controller Microcontrollers and processors; File Size995KB，128 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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PSD834F2VA-15JT Overview

256KX8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52, ROHS COMPLIANT, PLASTIC, LCC-52

PSD834F2VA-15JT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	LCC
package instruction	QCCJ, LDCC52,.8SQ
Contacts	52
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	1.5e-7 ns
JESD-30 code	S-PQCC-J52
length	19.1 mm
Number of I/O lines	27
Number of ports	4
Number of terminals	52
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
ROM size (bits)	2359296 Bits
Maximum seat height	4.57 mm
Maximum standby current	0.0001 A
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
UV erasable	N
width	19.1 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

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PSD8XXFX

Flash in-system programmable (ISP)

peripherals for 8-bit MCUs, 5 V

Features

■

Flash in-system programmable (ISP)

peripheral for 8-bit MCUs

Dual bank Flash memories

– Up to 2 Mbit of primary Flash memory (8

uniform sectors, 32K x8)

– Up to 256 Kbit secondary Flash memory (4

uniform sectors)

– Concurrent operation: read from one

memory while erasing and writing the other

Up to 256 Kbit SRAM

27 reconfigurable I/Oports

Enhanced

JTAG

serial port

PLD with macrocells

– Over 3000 gates of PLD: CPLD and DPLD

– CPLD with 16 output macrocells (OMCs)

and 24 input macrocells (IMCs)

– DPLD - user defined internal chip select

decoding

27 individually configurable I/O port pins

They can be used for the following functions:

– MCU I/Os

– PLD I/Os

– Latched MCU address output

– Special function I/Os.

– 16 of the I/O ports may be configured as

open-drain outputs.

In-system programming (ISP) with JTAG

– Built-in JTAG compliant serial port allows

full-chip in-system programmability

– Efficient manufacturing allow easy product

testing and programming

– Use low cost FlashLINK cable with PC

Page register

– Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

■

PQFP52 (M)

■

PLCC52 (J)

TQFP64 (U)

■

Programmable power management

Packages are ECOPACK

Device summary

Part number

PSD813F2

PSD813F4

PSD813F5

PSD8XXFX

PSD833F2

PSD834F2

PSD853F2

PSD854F2

Table 1.

Reference

■

May 2009

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www.st.com

Contents

PSD8XXFX

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24

Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.1

6.2

6.3

Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Description of primary Flash memory and secondary Flash memory . . . 27

Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3.1

6.3.2

Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reading the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Contents

7.8

7.9

7.10

Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Erase timeout flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1

8.2

8.3

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) . . 36

Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1

9.2

9.3

9.4

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10.1

10.2

10.3

Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . 41

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12.1

12.2

12.3

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Memory select configuration for MCUs with separate program and data

spaces 43

Configuration modes for MCUs with separate program and data spaces 44

12.3.1

12.3.2

Separate Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Combined Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

14.1

14.2

14.3

The Turbo Bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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Contents

PSD8XXFX

14.4

14.5

14.6

14.7

14.8

14.9

Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Loading and reading the Output macrocells (OMC) . . . . . . . . . . . . . . . . . 54

The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

15.1

15.2

15.3

15.4

15.5

15.6

15.7

15.8

PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 60

Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

16.1

16.2

16.3

16.4

16.5

16.6

16.7

16.8

16.9

General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

16.10 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

16.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

16.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

16.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

16.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

16.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

16.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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16.17 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

16.18 Input macro (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

16.19 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

16.20 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . 75

16.21 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

16.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

16.23 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

17.1

17.2

17.3

17.4

17.5

17.6

17.7

Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 80

For users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 85

18.1

18.2

18.3

18.4

Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 85

Reset of Flash memory erase and program cycles (on the PSD834Fx) . 85

Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 87

19.1

19.2

19.3

Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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