SP5658
2.7GHz 3-Wire Bus Controlled Frequency Synthesiser
Advance Information
DS4064
ISSUE 4.2
November 2001
The SP5658 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz.
The RF preamplifer contains a divide by two prescaler
which can be disabled for applications up to 2GHz so enabling
a step size equal to the comparison frequency up to 2GHz and
twice the comparison frequency up to 2.7GHz.
Comparison frequencies are obtained either from a crystal
controlled on–chip oscillator or from an external source.
The device contains two switching ports, in the 14 pin
version and four in the 16 pin, together with an ‘‘in–lock” flag
output. The device also contains a varactor line disable and
charge pump disable facility.
Ordering Information
SP5658F/KG/MP1S (Tubes, 14 lead SO)
SP5658S/KG/MP2S (Tubes, 16 lead SO)
SP5658F/KG/MP1T (Tape & Reel, 14 lead SO)
SP5658S/KG/MP2T (Tape & Reel, 16 lead SO)
CHARGE PUMP
CRYSTAL
1
14
DRIVE
V
EE
ENABLE
DATA
CLOCK
PORT P3
PORT P2
SP5658S
FEATURES
s
Complete 2.7GHz single chip system
s
Optimised for low phase noise
s
Selectable divide by two prescaler
s
Selectable reference division ratio
s
Charge pump disable
s
Varactor line disable
s
‘In–lock’ flag
s
Two switching ports in 14 pin version
s
Four switching ports in 16 pin version
s
Pin compatible with SP5659 I 2 C bus low
phase noise synthesiser
s
ESD protection (Normal ESD handling procedures
should be observed)
APPLICATIONS
s
SAT, TV, VCR and Cable tuning systems
s
Communications systems
DISABLE
ENABLE
DATA
CLOCK
PORT P1/OC
SP5658F
RF INPUT
RF INPUT
V
CC
LOCK
PORT P0/OP
MP14
CHARGE PUMP
CRYSTAL
DISABLE
1
16
DRIVE
V
EE
RF INPUT
RF INPUT
V
CC
LOCK
PORT P0/OP
PORT P1/OC
MP16
Fig. 1 Pin connections – top view
Advance Information
ELECTRICAL CHARACTERISTICS
SP5658
T amb = –20°C to + 80°C, V
CC
= + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise
stated.
Value
Characteristics
Pin
(SP5658S)
Units
Min
Typ
59
52
40
Max
74
65
300
mA
mA
mV
rms
V
CC
=5V Prescaler enabled, DE=1
V
CC
=5V Prescaler disabled, DE=0
300MHz to 2.7GHz Prescaler
enabled, DE=1, See Fig. 5b
80MHz Prescaler enabled,
DE=1, See Fig. 5b.
100MHz to 2.0GHz Prescaler
disabled, DE=0, See Fig. 5a
80MHz Prescaler disabled,
DE=0, See Fig. 5a.
Refer to Fig. 4
Refer to Fig. 4
Conditions
Supply current, I
CC
12
RF input voltage
13, 14
13,14
100
300
mV
rms
13, 14
40
300
mV
rms
13,14
50
300
mV
rms
Ω
pF
RF input impedance
RF input capacitance
Data, Clock, Enable & Disable
Input high voltage
Input low voltage
Input high current
Input low current
Clock Rate
Clock data & enable input
hysteresis
13, 14
13, 14
3,4,5,6
3
0
2
50
V
CC
0.7
10
–10
V
V
µA
µA
kHz
V
Input voltage = V
CC
Input voltage = V
EE
6
4,5,6
0.4
500
3
SP5658
Advance Information
ELECTRICAL CHARACTERISTICS
T amb = –20°C to + 80°C, V
CC
= + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed
by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristics
Pin
(SP5658S)
Min
Bus Timing
Data set up,
t
SU
Data hold,
t
HD
Enable set up,
t
ES
Enable hold,
t
EH
Clock to enable,
t
CE
Charge pump output current
Charge pump output leakage
Charge pump drive output
current
Oscillator temperature stability
Oscillator supply voltage
stability
External reference input
frequency
External reference input
amplitude
Crystal frequency
Crystal oscillator drive level
Recommended crystal series
resistance
1
1
16
2
2
2
2
2
2
100
2
200
4
45
200
1
2
2
20
500
12
±
3
±
10
nA
mA
ppm/°C
ppm/V
MHz
mV
PP
MHz
mV
PP
Ω
Applies to 4MHz crystal only.
‘‘Parallel resonant” crystal. Figure
quoted is under all conditions
including start up.
Includes temperature and process
tolerances.
AC coupled sinewave
AC coupled sinewave
4,5,6
300
600
300
600
300
ns
ns
ns
ns
ns
See Fig. 3
See Fig. 3
See Fig. 3
See Fig. 3
See Fig. 3
See Table 3, V
PIN1
= 2V
V
PIN1
= 2V
V
PIN16
= 0.7V
Value
Typ
Max
Units
Conditions
Crystal oscillator negative
resistance
Comparison frequency
Phase noise at phase detector
2
400
2
–142
Ω
MHz
dBC/
Hz
6kHz loop BW, phase comparator
freq 250kHz. Figure measured @
1kHz offset, DSB (within loop band
width).
Prescaler disabled, DE=0
Prescaler enabled, DE=1
See Table 1
RF division ratio
240
480
131071
262142
Reference division ratio
Output ports P0–P3 #
Sink current
Leakage current
Lock output
Sink current
Leakage current
# Ports P2 and P3 are not available on the SP5658F.
11
1
10
mA
µA
7,8,9,10
10
10
mA
µA
V
PORT
=0.7V
V
PORT
=13.2V
V
LOCK
=0.7V, ‘out of lock’
‘in lock’
4
Advance Information
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V EE at 0V
SP5658
Characteristics
Pin
(SP5658S)
Min
Max
Units
Conditions
Supply voltage, V
CC
RF input voltage
RF input DC offset
Port voltage
Total port current
Lock output DC offset
Charge pump DC offset
Drive DC offset
Crystal DC offset
Data, Clock, Enable & Disable DC
offset
Storage temperature
Junction temperature
MP14 Thermal Resistance
Chip to ambient 123
°C/W
Chip to case 45
°C/W
MP16 Thermal Resistance
Chip to ambient
Chip to case
Power consumption at V
CC
=5.5V
ESD protection
12
13, 14
13, 14
7 – 10
7 – 10
7 – 10
11
1
16
2
3–6
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
7
2.5
V
CC
+0.3
14
6
50
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
+125
150
V
V
p–p
V
V
V
mA
V
V
V
V
V
°C
°C
AC coupled as per application
Port in off state
Port in on state
111
41
407
ALL
2
°C/W
°C/W
mW
kV
All ports off, prescaler enabled
MIL–STD 883 TM 3015
FUNCTIONAL DESCRIPTION
The SP5658 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local
oscillator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high
comparison frequency and is fabricated in high speed logic,
which enables the generation of a loop with good phase noise
performance. The RF preamplifier contains a selectable
divide by two for operation above 2.0GHz. Up to 2GHz the RF
input interfaces directly with the programmable divider, so
eliminating degradation in phase noise due to the prescaler
action. The block diagram is shown in Fig.2.
The SP5658 is controlled by a standard 3–wire bus
comprising data, clock and enable inputs. The programming
word for the 16 pin variant contains 28 bits, four of which are
used for port selection, 18 to set the programmable divider
ratio and enable/disable the prescaler, bit DE, three bits to
select the reference division ratio, bits R0–R2, one bit to set
charge pump current, bit C0, and the remaining two bits to
access test modes, bit T0, and to disable the varactor drive,
bit OS. The data word for 14 pin variant is identical to 16 pin
except 26 bits only are required, two of which are used for port
selection. The programming format is shown in Fig. 3.
The clock input is disabled by an enable low signal, data
is therefore only clocked into the internal shift registers during
an enable high and is loaded into the controlling buffers by an
enable high to low transition. This load is also synchronised
with the programmable divider so giving smooth fine tuning.
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
The output of the preamplifier is fed to the 2/1 selectable
prescaler and then to the 17 bit fully programmable divider,
which is of MN+A architecture. The M counter is 13 bit and the
A counter 4. If bit DE is set to a 0 the prescaler is disabled; Note
that the control function DE cannot be used dynamically.
The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and frequency
domain with the comparison frequency. This frequency is
derived either from the on board crystal controlled oscillator or
from an external source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 8 ratios as
described in Table 1.
The output of the phase comparator feeds the charge
pump and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates the
current pulses into the varactor line voltage. The charge pump
can be disabled to a high impedance state by the DISABLE
input. The varactor drive output can also be disabled by the OS
bit within the data word, so switching the external transistor
‘OFF’ and allowing an external voltage to be written to the
varactor line for tuner alignment purposes.
The phase comparator also drives the lock detect circuit
which generates a lock flag. ‘In–lock’ is indicated by a high
impedance state on the lock output.
The programmable divider output divided by 2, F
pd
/2 and
the comparison frequency, F
comp
can be switched to ports P0
and P1 respectively by switching the device into test mode.
The test modes are described in Table 2.
5
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