MT5C1008SOJ-55L/IT datasheet, PDF

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MT5C1008SOJ-55L/IT: DescriptionStandard SRAM, 128KX8, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32; Categorystorage storage; File Size240KB，17 Pages; ManufacturerMicross; Websitehttps://www.micross.com

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MT5C1008SOJ-55L/IT Overview

Standard SRAM, 128KX8, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32

MT5C1008SOJ-55L/IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Micross
Parts packaging code	SOJ
package instruction	SOJ, SOJ32,.44
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	45 ns
Other features	TTL COMPATIBLE INPUTS/OUTPUTS, 2V DATA RETENTION, BATTERY BACKUP, LOW POWER STANDBY
I/O type	COMMON
JESD-30 code	R-CDSO-J32
JESD-609 code	e0
length	21 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SOJ
Encapsulate equivalent code	SOJ32,.44
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.191 mm
Maximum standby current	0.001 A
Minimum standby current	2 V
Maximum slew rate	0.115 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.1125 mm

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SRAM

Austin Semiconductor, Inc.

128K x 8 SRAM

WITH DUAL CHIP ENABLE

AVAILABLE AS MILITARY

SPECIFICATIONS

•SMD 5962-89598

•MIL-STD-883

A16

A14

A12

DQ1

DQ2

DQ3

MT5C1008

PIN ASSIGNMENT

(Top View)

32-Pin DIP (C, CW)

32-Pin CSOJ (SOJ)

A15

CE2

WE\

A13

A11

OE\

A10

CE\

DQ8

DQ7

DQ6

DQ5

DQ4

A16

A14

A12

DQ1

DQ2

DQ3

32-Pin LCC (EC)

32-Pin SOJ (DCJ)

A15

CE2

WE\

A13

A11

OE\

A10

CE\

DQ8

DQ7

DQ6

DQ5

DQ4

FEATURES

•

High Speed: 12, 15, 20, 25, 30, 35, 45, 55 and 70 ns

Battery Backup: 2V data retention

Low power standby

High-performance, low-power CMOS process

Single +5V (+10%) Power Supply

Easy memory expansion with CE1\, CE2, and OE\

options.

• All inputs and outputs are TTL compatible

32-Pin LCC (ECA)

4 3 2 1 32 31 30

A16

A14

A12

DQ1

DQ2

DQ3

A15

CE2

WE\

A13

A11

OE\

A10

CE\

DQ8

DQ7

DQ6

DQ5

DQ4

OPTIONS

• Timing

12ns access

15ns access

20ns access

25ns access

35ns access

45ns access

55ns access

70ns access

• Package(s)•

Ceramic DIP (400 mil)

Ceramic DIP (600 mil)

Ceramic LCC

Ceramic Flatpack

Ceramic SOJ

• 2V data retention/low power

MARKING

-12 (contact factory)

-15

-20

-25

-35

-45

-55*

-70*

DQ1

A12

A14

A10

A15

CE2

32-Pin Flat Pack (F)

A13

A11

A10

CE1

DQ8

14 15 16 17 18 19 20

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

GENERAL DESCRIPTION

The MT5C1008 SRAM employs high-speed, low power

CMOS designs using a four-transistor memory cell, and are

fabricated using double-layer metal, double-layer polysilicon

technology.

For design flexibility in high-speed memory

applications, this device offers dual chip enables (CE1\, CE2)

and output enable (OE\). These control pins can place the

outputs in High-Z for additional flexibility in system design.

All devices operate from a single +5V power supply and all

inputs and outputs are fully TTL compatible.

Writing to these devices is accomplished when write

enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.

Reading is accomplished when WE\ and CE2 remain HIGH and

CE1\ and OE\ go LOW. The devices offer a reduced power

standby mode when disabled, allowing system designs to

achieve low standby power requirements.

The “L” version offers a 2V data retention mode, re-

ducing current consumption to 1mA maximum.

ECA

DCJ

SOJ

No. 111

No. 112

No. 207

No. 208

No. 303

No. 501

No. 507

*Electrical characteristics identical to those provided for the 45ns

access devices.

For more products and information

please visit our web site at

www.austinsemiconductor.com

MT5C1008

Rev. 6.0 2/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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