M58BW032BT, M58BW032BB
M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst)
3.3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■
■
■
SUPPLY VOLTAGE
– V
DD
= 3.0V to 3.6V for Program, Erase
and Read
– V
DDQ
= V
DDQIN
= 1.6V to 3.6V for I/O
Buffers
HIGH PERFORMANCE
– Access Time: 45, 55 and 60ns
– 75MHz Effective Zero Wait-State Burst
Read
– Synchronous Burst Reads
– Asynchronous Page Reads
MEMORY ORGANIZATION
– Eight 64 Kbit small parameter Blocks
– Four 128Kbit large parameter Blocks (of
which one is OTP)
– Sixty-two 512Kbit main Blocks
Figure 1. Packages
PQFP80 (T)
BGA
■
■
■
■
■
■
HARDWARE BLOCK PROTECTION
– WP pin Lock Program and Erase
– V
PEN
signal for Program/Erase Enable
SOFTWARE BLOCK PROTECTION
– Tuning Protection to Lock Program and
Erase with 64-bit User Programmable
Password (M58BW032B version only)
SECURITY
– 64-bit Unique Device Identifier (UID)
FAST PROGRAMMING
– Write to Buffer and Program capability
OPTIMIZED FOR FDI DRIVERS
– Common Flash Interface (CFI)
– Fast Program/Erase Suspend feature in
each block
LOW POWER CONSUMPTION
– 100µA Typical Standby
LBGA80 (ZA)
10 x 8 ball array
■
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M58BW032xT: 8838h
– Bottom Device Code M58BW032xB:
8837h
OPERATING TEMPERATURE RANGE
– Automotive (Grade 3):
–
40 to 125°C
– Industrial (Grade 6):
–
40 to 90°C
November 2004
1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SUMMARY DESCRIPTION
The M58BW032B/D is a 32Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a Double-
Word basis using a 3.0V to 3.6V V
DD
supply for the
circuit and a V
DDQ
supply down to 1.6V for the In-
put and Output buffers.
The devices support Asynchronous (Latch Con-
trolled and Page Read) and Synchronous Bus op-
erations. The Synchronous Burst Read Interface
allows a high data transfer rate controlled by the
Burst Clock, K, signal. It is capable of bursting
fixed or unlimited lengths of data. The burst type,
latency and length are configurable and can be
easily adapted to a large variety of system clock
frequencies and microprocessors. All Writes are
Asynchronous. On power-up the memory defaults
to Read mode with an Asynchronous Bus.
The device features an asymmetrical block archi-
tecture. The M58BW032B/D has an array of 62
main blocks of 512 Kbits each, plus 4 large param-
eter blocks of 128Kbits each and 8 small parame-
ter blocks of 64 Kbits each. The large and small
parameter blocks are located either at the top
(M58BW032BT, M58BW032DT) or at the bottom
(M58BW032BB, M58BW032DB) of the address
space. The first large parameter block is referred
to as Boot Block and can be used either to store a
boot code or parameters.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
All blocks are protected during power-up. The
M58BW032B features four different levels of hard-
ware and software block protection to avoid un-
wanted program/erase operations:
■
Write/Protect Enable input, WP, provides a
hardware protection of a combination of
blocks from program or erase operations. The
Block Protection configuration can be defined
individually by issuing a Set Block Protection
Configuration Register or Clear Block
Protection Configuration Register commands.
■
All Program or Erase operations are blocked
when Reset, RP, is held low.
■
A Program/Erase Enable input, V
PEN
, is used
to protect all blocks, preventing Program and
Erase operations from affecting their data.
■
The Program and Erase commands can be
password protected by the Tuning Protection
command.
The M58BW032D offers the same protection fea-
tures with the exception of the Tuning Block Pro-
tection which is disabled in the factory.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consump-
tion is reduced to the standby level, the device is
write protected and both the Status and Burst Con-
figuration Registers are cleared. A recovery time is
required when the RP input goes High.
A manufacturer and device code are available.
They can be read from the memory allowing pro-
gramming equipment or applications to automati-
cally match their interface to the characteristics of
the memory.
Finally, the M58BW032B/D features a Unique De-
vice Identifier (UID) which is programmed by ST. It
is unique for each die and can be used to imple-
ment cryptographic algorithms to improve securi-
ty.
The memory is offered in PQFP80 (14 x 20mm)
and LBGA80 (1.0mm pitch) packages and it is
supplied with all the bits erased (set to ’1’).
2/9
Embedded System
京公网安备 11010802033920号
EEWORLD
